公开(公告)号：US20200350238A1

公开(公告)日：2020-11-05

申请号：US16402486

申请日：2019-05-03

Applicant: Infineon Technologies AG

Inventor： Chii Shang Hong ,  Wei Han Koo ,  Chiew Li Tai

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip, having a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and one or more supports connected between the first segment and the second segment, and an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from an upper surface of the encapsulant. A lower surface of the second segment is flush against the first bond pad.

公开(公告)号：US12094793B2

公开(公告)日：2024-09-17

申请号：US18380276

申请日：2023-10-16

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Chii Shang Hong ,  Teck Sim Lee ,  Bernd Schmoelzer ,  Ke Yan Tean ,  Lee Shuang Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L23/3121 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49506 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49838 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L23/49503 ,  H01L23/49575 ,  H01L2924/181

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

公开(公告)号：US11908771B2

公开(公告)日：2024-02-20

申请号：US17524879

申请日：2021-11-12

Applicant: Infineon Technologies AG

Inventor： Jayaganasan Narayanasamy ,  Angel Enverga ,  Chii Shang Hong ,  Chee Ming Lam ,  Sanjay Kumar Murugan ,  Subaramaniym Senivasan

IPC: H01L23/433 ,  H01L23/495 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/4334 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49811 ,  H01L24/84 ,  H01L23/49513 ,  H01L24/32 ,  H01L24/40 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/40175 ,  H01L2224/73263

Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.

公开(公告)号：US20230154827A1

公开(公告)日：2023-05-18

申请号：US17524879

申请日：2021-11-12

Applicant: Infineon Technologies AG

Inventor： Jayaganasan Narayanasamy ,  Angel Enverga ,  Chii Shang Hong ,  Chee Ming Lam ,  Sanjay Kumar Murugan ,  Subaramaniym Senivasan

IPC: H01L23/433 ,  H01L23/495

CPC classification number: H01L23/4334 ,  H01L23/49568 ,  H01L24/40

Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.

公开(公告)号：US10978380B2

公开(公告)日：2021-04-13

申请号：US16402486

申请日：2019-05-03

Applicant: Infineon Technologies AG

Inventor： Chii Shang Hong ,  Wei Han Koo ,  Chiew Li Tai

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip, having a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and one or more supports connected between the first segment and the second segment, and an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from an upper surface of the encapsulant. A lower surface of the second segment is flush against the first bond pad.

公开(公告)号：US20200350272A1

公开(公告)日：2020-11-05

申请号：US16575006

申请日：2019-09-18

Applicant: Infineon Technologies AG

Inventor： Chii Shang Hong ,  Ivan Nikitin ,  Wei Han Koo ,  Chiew Li Tai

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.

公开(公告)号：US11942383B2

公开(公告)日：2024-03-26

申请号：US17501568

申请日：2021-10-14

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Chii Shang Hong ,  Teck Sim Lee ,  Ralf Otremba ,  Daniel Pedone ,  Bernd Schmoelzer

IPC: H01L23/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L23/16 ,  H01L21/4871 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3672

Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.

公开(公告)号：US11876028B2

公开(公告)日：2024-01-16

申请号：US17502082

申请日：2021-10-15

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Chii Shang Hong ,  Teck Sim Lee ,  Bernd Schmoelzer ,  Ke Yan Tean ,  Lee Shuang Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3121 ,  H01L21/56 ,  H01L23/49506 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49838 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L23/49503 ,  H01L23/49575 ,  H01L2924/181

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

公开(公告)号：US10971436B2

公开(公告)日：2021-04-06

申请号：US16440037

申请日：2019-06-13

Applicant: Infineon Technologies AG

Inventor： Thomas Stoek ,  Chii Shang Hong ,  Chiew Li Tai ,  Edmund Sales Cabatbat

IPC: H01L23/495 ,  H01L23/00

Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.

公开(公告)号：US10354943B1

公开(公告)日：2019-07-16

申请号：US16033756

申请日：2018-07-12

Applicant: Infineon Technologies AG

Inventor： Thomas Stoek ,  Chii Shang Hong ,  Chiew Li Tai ,  Edmund Sales Cabatbat

IPC: H01L23/495 ,  H01L23/00

Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.