SEMICONDUCTOR PACKAGE HAVING A DIE PAD AND AN ENCAPSULATION WITH TRENCHES AND METHOD FOR FABRICATING THE SAME

    公开(公告)号:US20240387305A1

    公开(公告)日:2024-11-21

    申请号:US18647712

    申请日:2024-04-26

    Abstract: A semiconductor package includes: a die pad having opposing first and second sides and lateral sides connecting the first and second sides; at least one semiconductor die arranged over the first side; an encapsulation including a first dielectric material and encapsulating the semiconductor die, the second side of the die pad being at least partially exposed from the encapsulation; and a contiguous isolation structure including a second dielectric material different from the first dielectric material and covering the second side of the die pad. The encapsulation includes at least one first trench arranged along at least a part of a contour of the second side of the die pad. The second side of the die pad includes at least one second trench arranged along at least a part of the contour of the second side of the die pad. The trenches are filled by the contiguous isolation structure.

    Three Level Interconnect Clip
    2.
    发明申请

    公开(公告)号:US20220139811A1

    公开(公告)日:2022-05-05

    申请号:US17086976

    申请日:2020-11-02

    Abstract: An interconnect clip includes a die attach pad that comp includes rises a die attach surface at an inner side of the interconnect clip, a heat dissipation pad that includes a heat dissipation surface at an outer side of the interconnect clip, and a lead contact pad that includes a lead contact surface at an inner side of the interconnect clip or at an outer side of the interconnect clip. The outer side of the interconnect clip in the lead contact pad faces and is spaced apart from the inner side of the interconnect clip in the heat dissipation pad, and the inner side of the interconnect clip in the lead contact pad faces and is spaced apart from the outer side of the interconnect clip in the die attach pad.

    Three level interconnect clip
    4.
    发明授权

    公开(公告)号:US12057376B2

    公开(公告)日:2024-08-06

    申请号:US17086976

    申请日:2020-11-02

    Abstract: An interconnect clip includes a die attach pad that comp includes rises a die attach surface at an inner side of the interconnect clip, a heat dissipation pad that includes a heat dissipation surface at an outer side of the interconnect clip, and a lead contact pad that includes a lead contact surface at an inner side of the interconnect clip or at an outer side of the interconnect clip. The outer side of the interconnect clip in the lead contact pad faces and is spaced apart from the inner side of the interconnect clip in the heat dissipation pad, and the inner side of the interconnect clip in the lead contact pad faces and is spaced apart from the outer side of the interconnect clip in the die attach pad.

    CLIPS FOR SEMICONDUCTOR PACKAGES
    5.
    发明申请

    公开(公告)号:US20210043549A1

    公开(公告)日:2021-02-11

    申请号:US16535632

    申请日:2019-08-08

    Abstract: A clip for a semiconductor package includes a first portion and a second portion. The first portion includes a first surface, a second surface opposite to the first surface and configured to contact a first electrically conductive component, and a stepped region between the first surface and the second surface such that the second surface has a smaller area than the first surface. The second portion is coupled to the first portion and configured to contact a second electrically conductive component. The second portion includes a third surface aligned with the first surface.

    CLIPS FOR SEMICONDUCTOR PACKAGES
    6.
    发明申请

    公开(公告)号:US20210013171A1

    公开(公告)日:2021-01-14

    申请号:US16507003

    申请日:2019-07-09

    Abstract: A clip for a semiconductor package and a semiconductor having a clip is disclosed. In one example, the clip includes a first planar portion, a plurality of first pillars, and a plurality of first solder balls. Each first pillar of the plurality of first pillars is coupled to the first planar portion. Each first solder ball of the plurality of first solder balls is coupled to a corresponding first pillar of the plurality of first pillars.

    HIGH VOLTAGE SEMICONDUCTOR PACKAGE WITH PIN FIT LEADS

    公开(公告)号:US20220336401A1

    公开(公告)日:2022-10-20

    申请号:US17234964

    申请日:2021-04-20

    Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad and comprising a first terminal facing away from the die pad and a second terminal facing and electrically connected to the die pad, an interconnect clip electrically connected to the first terminal, an encapsulant body of electrically insulating material that encapsulates the semiconductor die and the interconnect clip, and a first opening in the encapsulant body that exposes a surface of the interconnect clip, the encapsulant body comprises a lower surface, an upper surface opposite from the lower surface, and a first outer edge side extending between the lower surface and the upper surface, and the first opening is laterally offset from the first outer edge side.

    Clips for semiconductor packages
    9.
    发明授权

    公开(公告)号:US11211353B2

    公开(公告)日:2021-12-28

    申请号:US16507003

    申请日:2019-07-09

    Abstract: A clip for a semiconductor package and a semiconductor having a clip is disclosed. In one example, the clip includes a first planar portion, a plurality of first pillars, and a plurality of first solder balls. Each first pillar of the plurality of first pillars is coupled to the first planar portion. Each first solder ball of the plurality of first solder balls is coupled to a corresponding first pillar of the plurality of first pillars.

    Semiconductor package with space efficient lead and die pad design

    公开(公告)号:US11069600B2

    公开(公告)日:2021-07-20

    申请号:US16422163

    申请日:2019-05-24

    Abstract: A semiconductor package includes a die pad having a die attach surface, a rear surface opposite the die attach surface, and an outer edge side extending between the die attach surface and the rear surface, the outer edge side having a step-shaped profile, wherein an upper section of the die pad laterally overhangs past a lower section of the die pad, a semiconductor die mounted on the die attach surface and having a first electrical terminal on an upper surface of the semiconductor die, and a first conductive clip that directly electrically contacts the first electrical terminal and wraps around the outer edge side of the die pad such that a section of the first conductive clip is at least partially within an area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.

Patent Agency Ranking