公开(公告)号：US11581194B2

公开(公告)日：2023-02-14

申请号：US17167620

申请日：2021-02-04

Applicant: Infineon Technologies AG

Inventor： Frederik Otto ,  Paul Frank

IPC: H01L21/324 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56

Abstract: An electronic device comprises a semiconductor die, a layer stack disposed on the semiconductor die and comprising one or more functional layers, wherein the layer stack comprises a protection layer which is an outermost functional layer of the layer stack, and a sacrificial layer disposed on the protection layer, wherein the sacrificial layer comprises a material which decomposes or becomes volatile at a temperature between 100° and 400° C.

公开(公告)号：US11329021B2

公开(公告)日：2022-05-10

申请号：US16685318

申请日：2019-11-15

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez ,  Fabian Craes ,  Barbara Eichinger ,  Martin Mischitz ,  Frederik Otto ,  Fabien Thion

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/428 ,  H01L21/782

Abstract: A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.

公开(公告)号：US20240162129A1

公开(公告)日：2024-05-16

申请号：US18504309

申请日：2023-11-08

Applicant: Infineon Technologies AG

Inventor： Christoph Bayer ,  Michael Fügl ,  Frank Singer ,  Thorsten Meyer ,  Fabian Craes ,  Andreas Grassmann ,  Frederik Otto

IPC: H01L23/498 ,  B82Y10/00 ,  H01L23/00 ,  H01L23/31 ,  H01L25/07

CPC classification number: H01L23/49811 ,  B82Y10/00 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/49844 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/072 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/181

Abstract: A substrate arrangement includes: a first metallization layer, nanowires arranged on a surface of the first metallization layer; and a component arranged on the first metallization layer such that a first subset of the nanowires is arranged between the first metallization layer and the component. The nanowires are evenly distributed over a section of the surface area or over the entire surface area of the first metallization layer. Each nanowire includes first and second ends. The first end of each nanowire is inseparably connected to the surface of the first metallization layer. The second end of each nanowire of the first subset is inseparably connected to a surface of one of the component such that the first subset of nanowires forms a permanent connection between the first metallization layer and the component. There are fewer nanowires in the first subset of nanowires than there are total nanowires.

公开(公告)号：US09659793B2

公开(公告)日：2017-05-23

申请号：US14943511

申请日：2015-11-17

Applicant: Infineon Technologies AG

Inventor： Nicolas Heuck ,  Frederik Otto ,  Christian Steininger

IPC: H01L21/00 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L21/4825 ,  H01L21/4842 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/27003 ,  H01L2224/27005 ,  H01L2224/2732 ,  H01L2224/2744 ,  H01L2224/27442 ,  H01L2224/27848 ,  H01L2224/29294 ,  H01L2224/29295 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29364 ,  H01L2224/29369 ,  H01L2224/29373 ,  H01L2224/2939 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/75252 ,  H01L2224/75315 ,  H01L2224/75343 ,  H01L2224/75745 ,  H01L2224/83048 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/832 ,  H01L2224/83203 ,  H01L2224/83207 ,  H01L2224/83208 ,  H01L2224/8322 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8384 ,  H01L2224/83986 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A method for producing a material-bonding connection between a semiconductor chip and a metal layer is disclosed. For this purpose, a semiconductor chip, a metal layer, which has a chip mounting portion, and also a bonding medium containing a metal powder are provided. The metal powder is sintered in a sintering process. In this case, throughout a prescribed sintering time, the prescribed requirements are met, that the bonding medium is arranged between the semiconductor chip and the metal layer and extends right through from the semiconductor chip to the metal layer, that the semiconductor chip and the metal layer are pressed against one another in a pressing-pressure range that lies above a minimum pressing pressure, that the bonding medium is kept in a temperature range that lies above a minimum temperature and that a sound signal is introduced into the bonding medium.

公开(公告)号：US20160148819A1

公开(公告)日：2016-05-26

申请号：US14943511

申请日：2015-11-17

Applicant: Infineon Technologies AG

Inventor： Nicolas Heuck ,  Frederik Otto ,  Christian Steininger

IPC: H01L21/48

CPC classification number: H01L21/4825 ,  H01L21/4842 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/27003 ,  H01L2224/27005 ,  H01L2224/2732 ,  H01L2224/2744 ,  H01L2224/27442 ,  H01L2224/27848 ,  H01L2224/29294 ,  H01L2224/29295 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29364 ,  H01L2224/29369 ,  H01L2224/29373 ,  H01L2224/2939 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/75252 ,  H01L2224/75315 ,  H01L2224/75343 ,  H01L2224/75745 ,  H01L2224/83048 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/832 ,  H01L2224/83203 ,  H01L2224/83207 ,  H01L2224/83208 ,  H01L2224/8322 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8384 ,  H01L2224/83986 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A method for producing a material-bonding connection between a semiconductor chip and a metal layer is disclosed. For this purpose, a semiconductor chip, a metal layer, which has a chip mounting portion, and also a bonding medium containing a metal powder are provided. The metal powder is sintered in a sintering process. In this case, throughout a prescribed sintering time, the prescribed requirements are met, that the bonding medium is arranged between the semiconductor chip and the metal layer and extends right through from the semiconductor chip to the metal layer, that the semiconductor chip and the metal layer are pressed against one another in a pressing-pressure range that lies above a minimum pressing pressure, that the bonding medium is kept in a temperature range that lies above a minimum temperature and that a sound signal is introduced into the bonding medium.

Abstract translation: 公开了一种用于在半导体芯片和金属层之间制造材料接合连接的方法。 为此，提供了具有芯片安装部分的半导体芯片，金属层以及含有金属粉末的接合介质。 金属粉末在烧结过程中烧结。 在这种情况下，在规定的烧结时间内，满足规定的要求，接合介质配置在半导体芯片和金属层之间，从半导体芯片向右延伸到金属层，半导体芯片和金属 层压在超过最小压制压力的压制压力范围内，使粘合介质保持在高于最低温度的温度范围内并且声音信号被引入粘合介质中。

公开(公告)号：US20200161269A1

公开(公告)日：2020-05-21

申请号：US16685318

申请日：2019-11-15

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez ,  Fabian Craes ,  Barbara Eichinger ,  Martin Mischitz ,  Frederik Otto ,  Fabien Thion

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/428

Abstract: A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.