Semiconductor Module with Liquid Dielectric Encapsulant

    公开(公告)号:US20230360989A1

    公开(公告)日:2023-11-09

    申请号:US17737486

    申请日:2022-05-05

    Abstract: A semiconductor module includes a power electronics carrier including a metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a volume of electrically insulating encapsulant that fills the interior volume and encapsulates the power semiconductor die, and a pressure compensation element disposed on or within the electrically insulating encapsulant, wherein the electrically insulating encapsulant is a liquid, wherein the semiconductor module forms an impermeable seal that contains the volume of electrically insulating encapsulant, and wherein the pressure compensation element is configured to maintain the electrically insulating encapsulant at a substantially constant pressure during thermal expansion and thermal contraction of the electrically insulating encapsulant.

    Ultrasonic joining method and arrangement

    公开(公告)号:US11318688B2

    公开(公告)日:2022-05-03

    申请号:US16803201

    申请日:2020-02-27

    Abstract: A method for joining at least two joining partners includes performing a plurality of ultrasonic joining operations in direct succession, wherein performing an individual ultrasonic joining operation includes, with a second joining tool, applying pressure to a second joining partner arranged adjacent to a first joining partner, thereby pressing the second joining partner against the first joining partner, and, with the second joining tool, applying high-frequency ultrasonic vibrations to the joining partners. The method further includes, during at least one intermediate time interval between two directly successive ultrasonic joining operations, at least one of actively cooling and heating the second joining tool.

    Semiconductor encapsulant strength enhancer

    公开(公告)号:US12218018B2

    公开(公告)日:2025-02-04

    申请号:US17726045

    申请日:2022-04-21

    Abstract: A semiconductor module includes a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a reinforcing structure contained within the interior volume and including a textured surface that is accessible by fluid, a volume of curable encapsulant disposed within the interior volume and encapsulating the power semiconductor die, wherein the reinforcing structure is embedded within the volume of curable encapsulant such that the textured surface adheres to the encapsulant, and wherein the reinforcing structure has a tensile strength that is greater than a tensile strength of the curable encapsulant.

    Ultrasonic Joining Method and Arrangement
    5.
    发明申请

    公开(公告)号:US20200282663A1

    公开(公告)日:2020-09-10

    申请号:US16803201

    申请日:2020-02-27

    Abstract: A method for joining at least two joining partners includes performing a plurality of ultrasonic joining operations in direct succession, wherein performing an individual ultrasonic joining operation includes, with a second joining tool, applying pressure to a second joining partner arranged adjacent to a first joining partner, thereby pressing the second joining partner against the first joining partner, and, with the second joining tool, applying high-frequency ultrasonic vibrations to the joining partners. The method further includes, during at least one intermediate time interval between two directly successive ultrasonic joining operations, at least one of actively cooling and heating the second joining tool.

    HOUSING, SEMICONDUCTOR MODULE AND METHODS FOR PRODUCING THE SAME

    公开(公告)号:US20250014952A1

    公开(公告)日:2025-01-09

    申请号:US18762949

    申请日:2024-07-03

    Inventor: Georg Troska

    Abstract: A housing for a power semiconductor module arrangement includes sidewalls and a top. The top includes a first layer of a first material having a plurality of openings, and a second layer of a second material that is different from the first material. The second material has a comparative tracking index (CTI) that is higher than a comparative tracking index of the first material. The second layer partly covers at least one of a bottom surface of the first layer and a top surface of the first layer, and/or the first layer includes at least one gap sealed by a section of the second layer such that the second layer forms at least one section of the housing.

    Semiconductor Encapsulant Strength Enhancer
    8.
    发明公开

    公开(公告)号:US20230343661A1

    公开(公告)日:2023-10-26

    申请号:US17726045

    申请日:2022-04-21

    CPC classification number: H01L23/26 H01L21/56 H01L23/296 H01L23/3121

    Abstract: A semiconductor module includes a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a reinforcing structure contained within the interior volume and including a textured surface that is accessible by fluid, a volume of curable encapsulant disposed within the interior volume and encapsulating the power semiconductor die, wherein the reinforcing structure is embedded within the volume of curable encapsulant such that the textured surface adheres to the encapsulant, and wherein the reinforcing structure has a tensile strength that is greater than a tensile strength of the curable encapsulant.

    Ultrasonic Joining Method and Arrangement

    公开(公告)号:US20220194023A1

    公开(公告)日:2022-06-23

    申请号:US17691255

    申请日:2022-03-10

    Abstract: A method for joining at least two joining partners includes performing a plurality of ultrasonic joining operations in direct succession, wherein performing an individual ultrasonic joining operation includes, with a second joining tool, applying pressure to a second joining partner arranged adjacent to a first joining partner, thereby pressing the second joining partner against the first joining partner, and, with the second joining tool, applying high-frequency ultrasonic vibrations to the joining partners. The method further includes, during at least one intermediate time interval between two directly successive ultrasonic joining operations, at least one of actively cooling and heating the second joining tool. The second joining tool is heated or cooled by a temperature unit. The temperature unit is inactive during each of the plurality of ultrasonic joining operations.

    Semiconductor substrate
    10.
    发明授权

    公开(公告)号:US11211307B2

    公开(公告)日:2021-12-28

    申请号:US16671541

    申请日:2019-11-01

    Abstract: A semiconductor substrate includes a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer. The dielectric insulation layer includes a first material having a thermal conductivity of between 25 and 180 W/mK, and an insulation strength of between 15 and 50 kV/mm, and an electrically conducting or semiconducting second material evenly distributed within the first material.

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