公开(公告)号：US12218018B2

公开(公告)日：2025-02-04

申请号：US17726045

申请日：2022-04-21

Applicant: Infineon Technologies AG

Inventor： Georg Troska ,  Hans Hartung

IPC: H01L23/26 ,  H01L21/56 ,  H01L23/00 ,  H01L23/053 ,  H01L23/16 ,  H01L23/24 ,  H01L23/29 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L25/07

Abstract: A semiconductor module includes a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a reinforcing structure contained within the interior volume and including a textured surface that is accessible by fluid, a volume of curable encapsulant disposed within the interior volume and encapsulating the power semiconductor die, wherein the reinforcing structure is embedded within the volume of curable encapsulant such that the textured surface adheres to the encapsulant, and wherein the reinforcing structure has a tensile strength that is greater than a tensile strength of the curable encapsulant.

公开(公告)号：US20240420968A1

公开(公告)日：2024-12-19

申请号：US18738124

申请日：2024-06-10

Applicant: Infineon Technologies AG

Inventor： Alexander Schmer ,  Anita Herzer ,  Hans Hartung ,  Martin Goldammer

IPC: H01L21/56 ,  H01L23/02 ,  H01L23/31 ,  H01L25/07

Abstract: A method for forming a power semiconductor module arrangement includes: arranging a housing on a substrate, the housing having sidewalls and being arranged to directly adjoin the substrate such that the substrate forms a ground surface of the housing; filling a liquid, viscous or semi-liquid UV-curable potting material into the housing so as to cover the substrate with the potting material; irradiating a first portion of the potting material in areas of the potting material near an interface between the substrate and the sidewalls so as to seal any gaps between the substrate and the sidewalls; and irradiating a second portion of the potting material farther away from the interface between the substrate and the sidewalls than the first portion of the potting material to form an encapsulant. Irradiation of the first and second portions of the potting material takes place at different times and/or via different radiation sources.

公开(公告)号：US20230360989A1

公开(公告)日：2023-11-09

申请号：US17737486

申请日：2022-05-05

Applicant: Infineon Technologies AG

Inventor： Georg Troska ,  Hans Hartung

IPC: H01L23/31 ,  H01L23/34 ,  H01L23/29 ,  H01L21/56

CPC classification number: H01L23/3142 ,  H01L23/34 ,  H01L23/3121 ,  H01L23/298 ,  H01L21/56 ,  H01L25/072

Abstract: A semiconductor module includes a power electronics carrier including a metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a volume of electrically insulating encapsulant that fills the interior volume and encapsulates the power semiconductor die, and a pressure compensation element disposed on or within the electrically insulating encapsulant, wherein the electrically insulating encapsulant is a liquid, wherein the semiconductor module forms an impermeable seal that contains the volume of electrically insulating encapsulant, and wherein the pressure compensation element is configured to maintain the electrically insulating encapsulant at a substantially constant pressure during thermal expansion and thermal contraction of the electrically insulating encapsulant.

公开(公告)号：US10134654B2

公开(公告)日：2018-11-20

申请号：US15660087

申请日：2017-07-26

Applicant: Infineon Technologies AG

Inventor： Hans Hartung ,  Reinhold Bayerer

IPC: H01L23/48 ,  H01L23/31 ,  H01L21/52 ,  H01L21/56 ,  H01L23/053 ,  H01L23/29 ,  H01L23/373 ,  H01L23/538 ,  H01L23/00 ,  H01L23/24 ,  H01L25/07

Abstract: One aspect relates to a power semiconductor module. The module includes a module housing, a substrate, and a semiconductor chip attached to the substrate. The semiconductor chip is disposed in the module housing. A dielectric first encapsulation is disposed in the module housing, in physical contact with both the semiconductor chip and the substrate and has a first modulus of elasticity. A dielectric second encapsulation is disposed in the module housing and has a second modulus of elasticity. The first encapsulation is a polymer and disposed between the substrate and the second encapsulation. The semiconductor chip is disposed between the first encapsulation and the substrate. Further, the first modulus of elasticity is greater than the second modulus of elasticity.

公开(公告)号：US20240071853A1

公开(公告)日：2024-02-29

申请号：US18140132

申请日：2023-04-27

Applicant: Infineon Technologies AG

Inventor： Hans Hartung ,  Martin Goldammer ,  Carsten Ehlers ,  Katja Engelkemeier ,  Guido Bönig

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/053 ,  H01L25/11

CPC classification number: H01L23/3135 ,  H01L21/56 ,  H01L23/053 ,  H01L24/48 ,  H01L25/115 ,  H01L2224/48091 ,  H01L2224/48225

Abstract: A power semiconductor module includes a power semiconductor die arranged on a power substrate, a housing enclosing the power semiconductor die and the power substrate, wherein an interior volume formed by the housing is divided by interior walls into at least a first compartment and a second compartment, wherein the power semiconductor die is arranged within the first compartment, a first encapsulation material encapsulating the power semiconductor die and at least partially filling the first compartment, and a second encapsulation material different from the first encapsulation material, the second encapsulation material encapsulating the first encapsulation material and at least partially filling the second compartment, wherein the first encapsulation material is arranged within the first compartment but not within the second compartment.

公开(公告)号：US20180033711A1

公开(公告)日：2018-02-01

申请号：US15660087

申请日：2017-07-26

Applicant: Infineon Technologies AG

Inventor： Hans Hartung ,  Reinhold Bayerer

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/373 ,  H01L23/538 ,  H01L21/56 ,  H01L21/52 ,  H01L23/053 ,  H01L23/29

CPC classification number: H01L23/3135 ,  H01L21/52 ,  H01L21/565 ,  H01L23/053 ,  H01L23/24 ,  H01L23/296 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/5386 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/072 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8384 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/16151 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2924/00

Abstract: One aspect relates to a power semiconductor module. The module includes a module housing, a substrate, and a semiconductor chip attached to the substrate. The semiconductor chip is disposed in the module housing. A dielectric first encapsulation is disposed in the module housing, in physical contact with both the semiconductor chip and the substrate and has a first modulus of elasticity. A dielectric second encapsulation is disposed in the module housing and has a second modulus of elasticity. The first encapsulation is a polymer and disposed between the substrate and the second encapsulation. The semiconductor chip is disposed between the first encapsulation and the substrate. Further, the first modulus of elasticity is greater than the second modulus of elasticity,

公开(公告)号：US20230343661A1

公开(公告)日：2023-10-26

申请号：US17726045

申请日：2022-04-21

Applicant: Infineon Technologies AG

Inventor： Georg Troska ,  Hans Hartung

IPC: H01L23/26 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/26 ,  H01L21/56 ,  H01L23/296 ,  H01L23/3121

Abstract: A semiconductor module includes a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a reinforcing structure contained within the interior volume and including a textured surface that is accessible by fluid, a volume of curable encapsulant disposed within the interior volume and encapsulating the power semiconductor die, wherein the reinforcing structure is embedded within the volume of curable encapsulant such that the textured surface adheres to the encapsulant, and wherein the reinforcing structure has a tensile strength that is greater than a tensile strength of the curable encapsulant.

公开(公告)号：US11211307B2

公开(公告)日：2021-12-28

申请号：US16671541

申请日：2019-11-01

Applicant: Infineon Technologies AG

Inventor： Georg Troska ,  Hans Hartung ,  Marianna Nomann

IPC: H01L23/373 ,  H01L23/15 ,  H01L25/07 ,  H01L23/498

Abstract: A semiconductor substrate includes a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer. The dielectric insulation layer includes a first material having a thermal conductivity of between 25 and 180 W/mK, and an insulation strength of between 15 and 50 kV/mm, and an electrically conducting or semiconducting second material evenly distributed within the first material.

公开(公告)号：US20150001700A1

公开(公告)日：2015-01-01

申请号：US13930607

申请日：2013-06-28

Applicant: Infineon Technologies AG

Inventor： Hans Hartung ,  Johannes Uhlig ,  Christian Domesle

IPC: H01L23/00 ,  H01L23/29 ,  H01L21/56

CPC classification number: H01L23/564 ,  H01L23/24 ,  H01L23/293 ,  H01L23/3135 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/072 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/206

Abstract: A module includes a base plate, a substrate having a first metallized side attached to the base plate and an opposing second metallized side, a power semiconductor die attached to the second metallized side of the substrate at a first side of the die, a first plurality of electrical connections between the second metallized side of the substrate and a second side of the die opposing the first side of the die, and a housing attached to a periphery of the base plate. The housing and base plate enclose the die and the first electrical connections. A second plurality of electrical connections extend from the second metallized side of the substrate through the housing to provide external electrical connections for the module. A parylene coating prevents gases and humidity from reaching the die, the first electrical connections, and the first metallized side of the substrate.

Abstract translation: 模块包括基板，具有附接到基板的第一金属化侧的基板和相对的第二金属化侧，在模具的第一侧附接到基板的第二金属化侧的功率半导体管芯，第一多个 在基板的第二金属化侧和与模具的第一侧相对的模具的第二侧之间的电连接以及附接到基板的周边的壳体。 外壳和底板封装模具和第一电气连接。 第二多个电连接从衬底的第二金属化侧通过壳体延伸以提供用于模块的外部电连接。 聚对二甲苯涂层防止气体和湿度到达模具，第一电连接和基板的第一金属化侧。