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    Charge pump arrangement and method for operating a charge pump arrangement
    1.
    发明授权
    Charge pump arrangement and method for operating a charge pump arrangement 有权

    公开(公告)号：US10483844B2

    公开(公告)日：2019-11-19

    申请号：US15851768

    申请日：2017-12-22

    Applicant: Infineon Technologies AG

    Inventor： Giacomo Curatolo

    IPC: H02M3/07 ,  G11C5/14

    Abstract: A charge pump arrangement and methods for operating a charge pump arrangement are disclosed. According to various embodiments, a charge pump arrangement may include: a charge pump circuit configured to convert an input voltage into an output voltage based on a pump clock signal; a feedback path configured to provide a feedback signal representing the output voltage of the charge pump circuit; and a control circuit configured to receive a clock signal and to control the output voltage of the charge pump circuit by controlling the pump clock signal based on the feedback signal and the clock signal.

    Resistive memory transition monitoring
    2.
    发明授权
    Resistive memory transition monitoring 有权

    公开(公告)号：US10311955B2

    公开(公告)日：2019-06-04

    申请号：US16058552

    申请日：2018-08-08

    Applicant: Infineon Technologies AG

    Inventor： Ulrich Backhausen ,  Giacomo Curatolo ,  Jens Rosenbusch

    IPC: G11C11/00 ,  G11C13/00 ,  G01R31/12 ,  G01R31/14 ,  G11C29/02 ,  G11C29/50

    Abstract: A method for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines. The method includes determining, by a current determining circuit, a cell current and a cell current change rate of at least one of the cells; determining, by a control circuit, whether the cell current change rate is outside of a cell current change rate predefined range; performing, by the control circuit, a predetermined action if the control circuit determination is positive; and storing, in a memory, the determined cell current at predetermined times, and to store the determined cell current change rate.

    Reuse of electrical charge at a semiconductor memory device
    3.
    发明授权
    Reuse of electrical charge at a semiconductor memory device 有权

    公开(公告)号：US09659657B2

    公开(公告)日：2017-05-23

    申请号：US14955628

    申请日：2015-12-01

    Applicant: Infineon Technologies AG

    Inventor： Leonardo Castro ,  Giacomo Curatolo

    IPC: G11C16/08 ,  G11C8/08

    CPC classification number: G11C16/08 ,  G11C8/08

    Abstract: A semiconductor memory device having a plurality of decoders, wherein each decoder is assigned to a select line, wherein no other decoder is assigned to the select line, each decoder has an output configured to charge the select line to when the decoder is activated and to discharge the select line when said decoder is deactivated. Also, each decoder is configured such that, in case that a first decoder gets deactivated after being activated and a second decoder of the decoders gets activated after being deactivated, the output of the first decoder and the output of the second decoder get connected to a common node for a predefined time interval, so that an electrical charge may be transferred from the select line, to the first decoder is assigned to, to the select line, to which the second decoder is assigned to, before the output of the first decoder gets connected to a reference voltage and the output of the second decoder gets connected to a supply voltage.

    Safe power up generating circuit having reset mechanism activating a chip select and command signal
    4.
    发明授权
    Safe power up generating circuit having reset mechanism activating a chip select and command signal 有权

    公开(公告)号：US11126234B2

    公开(公告)日：2021-09-21

    申请号：US16843194

    申请日：2020-04-08

    Applicant: Infineon Technologies AG

    Inventor： Giacomo Curatolo ,  Andreas Soukup

    IPC: G06F1/24 ,  G06F13/42

    Abstract: A method is provided for initializing an electronic circuit in dependence on an externally applied voltage. The electronic circuit contains a first input circuit and further circuit elements. In a first step, a first enable signal for the operation of the input circuit and a further enable signal for the operation of the further circuit elements are deactivated if the voltage falls below a first threshold. In a second step, the first enable signal for the operation of an input circuit is activated and the further enable signal for the operation of the further circuit elements is deactivated if the voltage exceeds the first threshold. This is followed by the reception, with the first input circuit, of a chip select signal for the activation of the electronic circuit and of a code word at a terminal for the command bus. The activation of the further enable signal for the operation of the further circuit elements takes place if the received chip select signal and the received code word have predetermined values.

    SAFE POWER UP MECHANISM
    5.
    发明申请
    SAFE POWER UP MECHANISM 审中-公开

    公开(公告)号：US20200326763A1

    公开(公告)日：2020-10-15

    申请号：US16843194

    申请日：2020-04-08

    Applicant: Infineon Technologies AG

    Inventor： Giacomo Curatolo ,  Andreas SOUKUP

    IPC: G06F1/24 ,  G06F13/42

    Abstract: A method is provided for initializing an electronic circuit in dependence on an externally applied voltage. The electronic circuit contains a first input circuit and further circuit elements. In a first step, a first enable signal for the operation of the input circuit and a further enable signal for the operation of the further circuit elements are deactivated if the voltage falls below a first threshold. In a second step, the first enable signal for the operation of an input circuit is activated and the further enable signal for the operation of the further circuit elements is deactivated if the voltage exceeds the first threshold. This is followed by the reception, with the first input circuit, of a chip select signal for the activation of the electronic circuit and of a code word at a terminal for the command bus. The activation of the further enable signal for the operation of the further circuit elements takes place if the received chip select signal and the received code word have predetermined values.

    Method and apparatus for controlling current in an array cell
    7.
    发明授权
    Method and apparatus for controlling current in an array cell 有权
    用于控制阵列单元中的电流的方法和装置

    公开(公告)号：US09558797B2

    公开(公告)日：2017-01-31

    申请号：US15095482

    申请日：2016-04-11

    Applicant: Infineon Technologies AG

    Inventor： Giacomo Curatolo ,  Wolf Allers

    IPC: G11C7/22 ,  G11C7/12 ,  G11C5/14 ,  G11C7/20

    CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/20

    Abstract: A method and an apparatus for controlling current in an array cell is disclosed. The method includes applying a supply voltage to a first access point of a transistor, precharging a second access point of the transistor to a predetermined voltage, applying a control voltage to a third access point of the transistor, and discharging the second access point of the transistor to turn on the transistor which causes a current flow through the array cell connected to the transistor.

    Abstract translation: 公开了一种用于控制阵列单元中的电流的方法和装置。 该方法包括将电源电压施加到晶体管的第一接入点，将晶体管的第二接入点预先充电至预定电压，将控制电压施加到晶体管的第三接入点，以及将晶体管的第二接入点 晶体管导通晶体管，其导致电流流过连接到晶体管的阵列单元。

    Circuit for injecting compensating charge in a bias line
    10.
    发明授权
    Circuit for injecting compensating charge in a bias line 有权

    公开(公告)号：US09892765B2

    公开(公告)日：2018-02-13

    申请号：US15095189

    申请日：2016-04-11

    Applicant: Infineon Technologies AG

    Inventor： Giacomo Curatolo ,  Leonardo Castro

    IPC: G11C7/06 ,  G05F3/26 ,  G11C7/02

    CPC classification number: G11C7/062 ,  G05F3/262 ,  G11C7/02 ,  G11C7/067 ,  G11C2207/063

    Abstract: According to one embodiment, a circuit is described including a circuit component configured to switch from a first state into a second state including a node whose potential changes by a predetermined voltage when the circuit component switches from the first state into the second state, a line coupled with the node wherein the switching of the circuit component from the first state into the second state draws or injects a predetermined charge from or into the line, a capacitor coupled to the line and a compensation circuit configured to generate a predetermined multiple of the predetermined voltage and to compensate the charge drawn from or injected into the line by driving the capacitor with the multiple of the predetermined voltage.

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