公开(公告)号：US09437593B2

公开(公告)日：2016-09-06

申请号：US14488020

申请日：2014-09-16

Applicant: Infineon Technologies AG

Inventor： Jiang Yan ,  Henning Haffner ,  Frank Huebinger ,  Sun-Oo Kim ,  Richard Lindsay ,  Klaus Schruefer

IPC: H01L21/70 ,  H01L27/06 ,  H01L23/525 ,  H01L29/06 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L27/0617 ,  H01L21/28088 ,  H01L23/5256 ,  H01L29/0653 ,  H01L29/4958 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer.

Abstract translation: 优选实施例包括制造熔丝元件的方法，该方法包括在半导体结构上形成多晶硅层，用碳或氮掺杂多晶硅层，在多晶硅层上沉积金属; 以及退火所述金属和多晶硅层以在所述多晶硅层的上部形成硅化物。

公开(公告)号：US20160118477A1

公开(公告)日：2016-04-28

申请号：US14983688

申请日：2015-12-30

Applicant: Infineon Technologies AG

Inventor： Juergen Holz ,  Klaus Schruefer ,  Helmut Tews

IPC: H01L29/66 ,  H01L21/283 ,  H01L29/417 ,  H01L21/3205 ,  H01L29/06 ,  H01L21/306 ,  H01L21/31

CPC classification number: H01L29/66636 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/3205 ,  H01L29/0653 ,  H01L29/41783

Abstract: A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region and along the sidewalls of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions.

Abstract translation: 一种制造具有局部源极/漏极绝缘的场效应晶体管的方法。 该方法包括在半导体衬底上形成和图案化具有栅极层和栅极电介质的栅叠层; 在半导体衬底中的栅极堆叠处形成源极和漏极凹陷; 至少在底部区域中并且沿着源极和漏极凹陷的侧壁形成凹陷绝缘层; 以及用用于实现源极和漏极区域的填充层填充所述至少部分绝缘的源极和漏极凹部。

公开(公告)号：US20140124827A1

公开(公告)日：2014-05-08

申请号：US14153947

申请日：2014-01-13

Applicant: Infineon Technologies AG

Inventor： Juergen Holz ,  Ronald Kakoschke ,  Thomas Nirschl ,  Christian Pacha ,  Klaus Schruefer ,  Thomas Schulz ,  Doris Schmitt-Landsiedel

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7392 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7854 ,  H01L29/7856

Abstract: Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Abstract translation: 集成电路装置，其包括场效应晶体管，特别是隧道场效应晶体管。 特别地，对于具有较厚的栅极电介质的隧道场效应晶体管与相同的集成电路装置上的其它晶体管相比较的解释。 作为替代或另外，所述隧道场效应晶体管具有在沟道形成区域的相对远侧的栅极区域或隧道场效应晶体管的连接区域之间的界面。

公开(公告)号：US20150001638A1

公开(公告)日：2015-01-01

申请号：US14488020

申请日：2014-09-16

Applicant: Infineon Technologies AG

Inventor： Jiang Yan ,  Henning Haffner ,  Frank Huebinger ,  Sun-Oo Kim ,  Richard Lindsay ,  Klaus Schruefer

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L27/0617 ,  H01L21/28088 ,  H01L23/5256 ,  H01L29/0653 ,  H01L29/4958 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer.

Abstract translation: 优选实施例包括制造熔丝元件的方法，该方法包括在半导体结构上形成多晶硅层，用碳或氮掺杂多晶硅层，在多晶硅层上沉积金属; 以及退火所述金属和多晶硅层以在所述多晶硅层的上部形成硅化物。

公开(公告)号：US09219063B2

公开(公告)日：2015-12-22

申请号：US14153947

申请日：2014-01-13

Applicant: Infineon Technologies AG

Inventor： Juergen Holz ,  Ronald Kakoschke ,  Thomas Nirschl ,  Christian Pacha ,  Klaus Schruefer ,  Thomas Schulz ,  Doris Schmitt-Landsiedel

IPC: H01L29/78 ,  H01L27/06 ,  H01L27/088 ,  H01L29/739 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/105 ,  H01L21/336 ,  H01L27/12

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7392 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7854 ,  H01L29/7856

Abstract: Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Abstract translation: 集成电路装置，其包括场效应晶体管，特别是隧道场效应晶体管。 特别地，对于具有较厚的栅极电介质的隧道场效应晶体管与相同的集成电路装置上的其它晶体管相比较的解释。 作为替代或另外，所述隧道场效应晶体管具有在沟道形成区域的相对远侧的栅极区域或隧道场效应晶体管的连接区域之间的界面。

公开(公告)号：US08952487B2

公开(公告)日：2015-02-10

申请号：US14188761

申请日：2014-02-25

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Barth ,  Andreas Rusch ,  Klaus Schruefer

IPC: H01L29/00 ,  H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An electronic circuit arrangement in accordance with some embodiments has a substrate, the substrate including: a plurality of metallization layers located one above the other; a single fuse-link via coupled between a first metallization layer and a second metallization layer of the plurality of metallization layers, wherein the single fuse-link via is in the form of an electrical fuse link preferentially programmable by applying a sufficiently large current to melt or degenerate the fuse link; a plurality of through-contact vias coupled in parallel between a third metallization layer and a fourth metallization layer of the plurality of metallization layers, wherein the through-contact vias form a through-contact between the third and fourth metallization layers; and electrical circuit components, arranged in a circuit layer, which are electrically coupled to one another by means of the single fuse-link via and by means of the plurality of through-contact vias.

Abstract translation: 根据一些实施例的电子电路装置具有基板，所述基板包括：多个金属化层，其位于彼此之上; 单个熔丝链路，其通过耦合在所述多个金属化层的第一金属化层和第二金属化层之间，其中所述单个熔丝连接通孔为电熔丝链的形式，所述熔丝链通过施加足够大的电流而熔化 或退化熔断体; 在所述多个金属化层的第三金属化层和第四金属化层之间并联耦合的多个通孔接触孔，其中所述通孔接触通孔在所述第三和第四金属化层之间形成通孔接触; 以及布置在电路层中的电路部件，其通过单个熔断体通过多个通孔接触通孔彼此电耦合。

公开(公告)号：US09012995B2

公开(公告)日：2015-04-21

申请号：US14047044

申请日：2013-10-07

Applicant: Infineon Technologies AG

Inventor： Ronald Kakoschke ,  Klaus Schruefer

IPC: H01L29/80 ,  H01L27/105 ,  H01L21/84 ,  H01L27/22 ,  H01L27/24 ,  H01L29/78 ,  H01L45/00 ,  H01L27/115

CPC classification number: H01L27/1052 ,  H01L21/84 ,  H01L27/115 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L29/41791 ,  H01L29/785 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141

Abstract: A memory element includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.

Abstract translation: 存储元件包括FinFET选择器件和存储元件。 在一些实施例中，存储器单元具有耦合在鳍片的表面和存储元件之间的接触元件。

公开(公告)号：US20140167215A1

公开(公告)日：2014-06-19

申请号：US14188761

申请日：2014-02-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Hans-Joachim Barth ,  Andreas Rusch ,  Klaus Schruefer

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An electronic circuit arrangement in accordance with some embodiments has a substrate, the substrate including: a plurality of metallization layers located one above the other; a single fuse-link via coupled between a first metallization layer and a second metallization layer of the plurality of metallization layers, wherein the single fuse-link via is in the form of an electrical fuse link preferentially programmable by applying a sufficiently large current to melt or degenerate the fuse link; a plurality of through-contact vias coupled in parallel between a third metallization layer and a fourth metallization layer of the plurality of metallization layers, wherein the through-contact vias form a through-contact between the third and fourth metallization layers; and electrical circuit components, arranged in a circuit layer, which are electrically coupled to one another by means of the single fuse-link via and by means of the plurality of through-contact vias.

Abstract translation: 根据一些实施例的电子电路装置具有基板，所述基板包括：多个金属化层，其位于彼此之上; 单个熔丝链路，其通过耦合在所述多个金属化层的第一金属化层和第二金属化层之间，其中所述单个熔丝连接通孔为电熔丝链的形式，所述熔丝链通过施加足够大的电流而熔化 或退化熔断体; 在所述多个金属化层的第三金属化层和第四金属化层之间并联耦合的多个通孔接触孔，其中所述通孔接触通孔在所述第三和第四金属化层之间形成通孔接触; 以及布置在电路层中的电路部件，其通过单个熔断体通过多个通孔接触通孔彼此电耦合。