公开(公告)号：US20140205233A1

公开(公告)日：2014-07-24

申请号：US14224877

申请日：2014-03-25

Applicant: Infineon Technologies AG

Inventor： Thomas Schulz

IPC: G02B6/12

CPC classification number: G02B6/12 ,  H01L31/0232 ,  H01L31/02325 ,  H01L31/103 ,  H01L31/105 ,  H01L31/107 ,  H01L31/165

Abstract: One embodiment provides an integrated circuit including a first non-planar structure and a waveguide configured to provide electromagnetic waves to the first non-planar structure. The first non-planar structure provides a first signal in response to at least some of the electromagnetic waves.

Abstract translation: 一个实施例提供了包括第一非平面结构和波导的集成电路，该波导被配置为向第一非平面结构提供电磁波。 第一非平面结构响应于至少一些电磁波提供第一信号。

公开(公告)号：US09219063B2

公开(公告)日：2015-12-22

申请号：US14153947

申请日：2014-01-13

Applicant: Infineon Technologies AG

Inventor： Juergen Holz ,  Ronald Kakoschke ,  Thomas Nirschl ,  Christian Pacha ,  Klaus Schruefer ,  Thomas Schulz ,  Doris Schmitt-Landsiedel

IPC: H01L29/78 ,  H01L27/06 ,  H01L27/088 ,  H01L29/739 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/105 ,  H01L21/336 ,  H01L27/12

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7392 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7854 ,  H01L29/7856

Abstract: Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Abstract translation: 集成电路装置，其包括场效应晶体管，特别是隧道场效应晶体管。 特别地，对于具有较厚的栅极电介质的隧道场效应晶体管与相同的集成电路装置上的其它晶体管相比较的解释。 作为替代或另外，所述隧道场效应晶体管具有在沟道形成区域的相对远侧的栅极区域或隧道场效应晶体管的连接区域之间的界面。

公开(公告)号：US20140203455A1

公开(公告)日：2014-07-24

申请号：US14225095

申请日：2014-03-25

Applicant: Infineon Technologies AG

Inventor： Thomas Schulz ,  Sergei Postnikov

IPC: H01L23/52

CPC classification number: H01L23/52 ,  H01L21/027 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.

Abstract translation: 公开了图形特征的方法，制造半导体器件的方法和半导体器件。 在一个实施例中，图案化特征的方法包括在第一材料层中形成特征的第一部分。 特征的第二部分形成在第一材料层中，并且特征的第三部分形成在第二材料层中。

公开(公告)号：US09659962B2

公开(公告)日：2017-05-23

申请号：US14221108

申请日：2014-03-20

Applicant: Infineon Technologies AG

Inventor： Thomas Schulz ,  Hongfa Luan

IPC: H01L21/84 ,  H01L29/66 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L29/66803 ,  H01L29/785

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.

公开(公告)号：US09310554B2

公开(公告)日：2016-04-12

申请号：US14224877

申请日：2014-03-25

Applicant: Infineon Technologies AG

Inventor： Thomas Schulz

IPC: G02B6/12 ,  H01L31/107 ,  G02B6/10 ,  G02B6/42 ,  H01L31/00 ,  G01J1/04 ,  H01L31/0232 ,  H01L31/103 ,  H01L31/105 ,  H01L31/16

CPC classification number: G02B6/12 ,  H01L31/0232 ,  H01L31/02325 ,  H01L31/103 ,  H01L31/105 ,  H01L31/107 ,  H01L31/165

Abstract: One embodiment provides an integrated circuit including a first non-planar structure and a waveguide configured to provide electromagnetic waves to the first non-planar structure. The first non-planar structure provides a first signal in response to at least some of the electromagnetic waves.

Abstract translation: 一个实施例提供了包括第一非平面结构和波导的集成电路，该波导被配置为向第一非平面结构提供电磁波。 第一非平面结构响应于至少一些电磁波提供第一信号。

公开(公告)号：US09230906B2

公开(公告)日：2016-01-05

申请号：US14225095

申请日：2014-03-25

Applicant: Infineon Technologies AG

Inventor： Thomas Schulz ,  Sergei Postnikov

IPC: H01L27/10 ,  H01L23/52 ,  H01L21/027 ,  H01L23/522

CPC classification number: H01L23/52 ,  H01L21/027 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.

Abstract translation: 公开了图形特征的方法，制造半导体器件的方法和半导体器件。 在一个实施例中，图案化特征的方法包括在第一材料层中形成特征的第一部分。 特征的第二部分形成在第一材料层中，并且特征的第三部分形成在第二材料层中。

公开(公告)号：US20140203366A1

公开(公告)日：2014-07-24

申请号：US14221108

申请日：2014-03-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Thomas Schulz ,  Hongfa Luan

IPC: H01L27/12

CPC classification number: H01L27/1211 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L29/66803 ,  H01L29/785

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.

Abstract translation: 公开了半导体器件及其制造方法。 互补的金属氧化物半导体（CMOS）器件包括PMOS晶体管，其具有包括第一参数的至少两个第一栅电极和具有包括第二参数的至少两个第二栅电极的NMOS晶体管，其中第二参数不同于第一参数 参数。 第一参数和第二参数可以包括PMOS和NMOS晶体管的栅电极材料的厚度或掺杂物分布。 至少两个第一栅电极和至少两个第二栅电极的第一和第二参数分别建立PMOS和NMOS晶体管的功函数。

公开(公告)号：US20140124827A1

公开(公告)日：2014-05-08

申请号：US14153947

申请日：2014-01-13

Applicant: Infineon Technologies AG

Inventor： Juergen Holz ,  Ronald Kakoschke ,  Thomas Nirschl ,  Christian Pacha ,  Klaus Schruefer ,  Thomas Schulz ,  Doris Schmitt-Landsiedel

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7392 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7854 ,  H01L29/7856

Abstract: Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Abstract translation: 集成电路装置，其包括场效应晶体管，特别是隧道场效应晶体管。 特别地，对于具有较厚的栅极电介质的隧道场效应晶体管与相同的集成电路装置上的其它晶体管相比较的解释。 作为替代或另外，所述隧道场效应晶体管具有在沟道形成区域的相对远侧的栅极区域或隧道场效应晶体管的连接区域之间的界面。