公开(公告)号：US20210167034A1

公开(公告)日：2021-06-03

申请号：US17149741

申请日：2021-01-15

Applicant: Infineon Technologies AG

Inventor： Manfred MENGEL ,  Alexander HEINRICH ,  Steffen ORSO ,  Thomas BEHRENS ,  Oliver EICHINGER ,  Lim FONG ,  Evelyn NAPETSCHNIG ,  Edmund RIEDL

IPC: H01L23/00 ,  B23K35/30 ,  B23K35/26 ,  B23K35/28 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/495 ,  B23K1/00

Abstract: A chip arrangement including: a chip including a chip back side; a substrate including a surface with a plating; and a zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy including, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc.

公开(公告)号：US20170323865A1

公开(公告)日：2017-11-09

申请号：US15659670

申请日：2017-07-26

Applicant: Infineon Technologies AG

Inventor： Manfred MENGEL ,  Alexander HEINRICH ,  Steffen ORSO ,  Thomas BEHRENS ,  Oliver EICHINGER ,  Lim FONG ,  Evelyn NAPETSCHNIG ,  Edmund RIEDL

IPC: H01L23/00 ,  B23K35/28 ,  B23K35/30 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/495 ,  B23K1/00 ,  C22C30/04 ,  B23K35/26

CPC classification number: H01L24/48 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/282 ,  B23K35/3013 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/05599 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/207

Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.

公开(公告)号：US20230117806A1

公开(公告)日：2023-04-20

申请号：US17952688

申请日：2022-09-26

Applicant: Infineon Technologies AG

Inventor： Thorsten MEYER ,  Thomas BEHRENS ,  Christian IRRGANG ,  Frank ZUDOCK

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/16 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/29

Abstract: Semiconductor packages and methods for manufacturing are disclosed. In one example, a method for manufacturing a semiconductor package includes providing an electrically conductive chip carrier including a mounting surface and a protrusion extending out of the mounting surface. At least one semiconductor chip is arranged on the mounting surface. The method further includes encapsulating the protrusion and the at least one semiconductor chip in an encapsulation material, wherein surfaces of the protrusion and the at least one semiconductor chip facing away from the mounting surface remain uncovered by the encapsulation material. An electrical redistribution layer is formed over the surfaces of the protrusion and the at least one semiconductor chip facing away from the mounting surface. The electrical redistribution layer provides an electrical connection between the protrusion and the at least one semiconductor chip.