公开(公告)号：US20170323865A1

公开(公告)日：2017-11-09

申请号：US15659670

申请日：2017-07-26

Applicant: Infineon Technologies AG

Inventor： Manfred MENGEL ,  Alexander HEINRICH ,  Steffen ORSO ,  Thomas BEHRENS ,  Oliver EICHINGER ,  Lim FONG ,  Evelyn NAPETSCHNIG ,  Edmund RIEDL

IPC: H01L23/00 ,  B23K35/28 ,  B23K35/30 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/495 ,  B23K1/00 ,  C22C30/04 ,  B23K35/26

CPC classification number: H01L24/48 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/282 ,  B23K35/3013 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/05599 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/207

Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.

公开(公告)号：US20220355422A1

公开(公告)日：2022-11-10

申请号：US17713857

申请日：2022-04-05

Applicant: Infineon Technologies AG

Inventor： Alexander ROTH ,  Catharina WILLE ,  Alexander HEINRICH

IPC: B23K35/36 ,  B32B15/01 ,  B23K35/02 ,  B23K1/00

Abstract: A lead-free solder material is provided. In one example, the solder material may include solder particles including at least 30 wt % nickel, and an activator including or consisting of at least one of a group of activator materials, the group including an organic acid or salt thereof, and an amine or salt thereof.

公开(公告)号：US20210167034A1

公开(公告)日：2021-06-03

申请号：US17149741

申请日：2021-01-15

Applicant: Infineon Technologies AG

Inventor： Manfred MENGEL ,  Alexander HEINRICH ,  Steffen ORSO ,  Thomas BEHRENS ,  Oliver EICHINGER ,  Lim FONG ,  Evelyn NAPETSCHNIG ,  Edmund RIEDL

IPC: H01L23/00 ,  B23K35/30 ,  B23K35/26 ,  B23K35/28 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/495 ,  B23K1/00

Abstract: A chip arrangement including: a chip including a chip back side; a substrate including a surface with a plating; and a zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy including, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc.

公开(公告)号：US20170317016A1

公开(公告)日：2017-11-02

申请号：US15497267

申请日：2017-04-26

Applicant: Infineon Technologies AG

Inventor： Alexander HEINRICH ,  Bernd GOLLER ,  Thorsten MEYER ,  Gerald OFNER

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: A package comprising a chip carrier, an electronic chip on the chip carrier, a clip on the electronic chip, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive vertical connection structure provided separately from the clip and electrically connecting the chip carrier with the clip.

公开(公告)号：US20160126216A1

公开(公告)日：2016-05-05

申请号：US14931021

申请日：2015-11-03

Applicant: Infineon Technologies AG

Inventor： Alexander HEINRICH ,  Hermann GRUBER

IPC: H01L23/00 ,  H01L21/683

CPC classification number: H01L24/83 ,  B23K20/023 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/75 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68354 ,  H01L2224/04026 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/2745 ,  H01L2224/2746 ,  H01L2224/27462 ,  H01L2224/29019 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29164 ,  H01L2224/29169 ,  H01L2224/30181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/33181 ,  H01L2224/75252 ,  H01L2224/7598 ,  H01L2224/83005 ,  H01L2224/83193 ,  H01L2224/83204 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/8383 ,  H01L2224/83894 ,  H01L2224/83898 ,  H01L2224/97 ,  H01L2924/00015 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3656 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/8384 ,  H01L2224/27505 ,  H01L2224/83815

Abstract: Various embodiments provide a method of forming an interconnection between an electric component and an electronic component, wherein the method comprises forming a first interconnection sublayer on an electric component, wherein the first interconnection sublayer comprises a metal and has a main surface opposite to the electric component, wherein the main surface has a first surface roughness; forming a second interconnection sublayer on an electronic component, wherein the second interconnection sublayer comprises the metal and has a surface opposite to the electronic component, wherein the surface has a second surface roughness, wherein the first surface roughness and the second surface roughness are in the same order of magnitude; and interconnecting the first interconnection sublayer and the second interconnection sublayer by contacting the same and applying pressure and heat to the contacted first and second interconnection sublayers.

Abstract translation: 各种实施例提供了一种在电气部件和电子部件之间形成互连的方法，其中所述方法包括在电气部件上形成第一互连子层，其中所述第一互连子层包括金属并且具有与所述电气部件相对的主表面 ，其中所述主表面具有第一表面粗糙度; 在电子部件上形成第二互连子层，其中所述第二互连子层包括所述金属并具有与所述电子部件相对的表面，其中所述表面具有第二表面粗糙度，其中所述第一表面粗糙度和所述第二表面粗糙度在 相同数量级; 并且通过使所述第一互连子层和所述第二互连子层接触所述第一互连子层和所述第二互连子层，并且将所述第一互连子层和所述第二互连子层与所接触的第一和第二互连子层施加压力和热量。

公开(公告)号：US20160126165A1

公开(公告)日：2016-05-05

申请号：US14927561

申请日：2015-10-30

Applicant: Infineon Technologies AG

Inventor： Paul FRANK ,  Alexander HEINRICH ,  Michael JUERSS ,  Chiong Yong TAY

IPC: H01L23/495 ,  H01L21/78 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L23/488 ,  H01L24/32 ,  H01L24/83 ,  H01L29/0657 ,  H01L2224/2929 ,  H01L2224/3207 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/32502 ,  H01L2224/83065 ,  H01L2224/83192 ,  H01L2924/014

Abstract: A method of connecting a substrate is provided, wherein the substrate may include a first main surface and a second main surface opposite the first main surface. The method may include forming at least one protrusion on the first main surface of the substrate, forming a fixing agent over the first main surface of the substrate and over the at least one protrusion; and arranging the substrate on a carrier. The at least one protrusion may contact a surface of the carrier and may be configured to keep the first main surface of the substrate at a distance to the contacted surface of the carrier corresponding to a height of the protrusion, thereby forming a space between the first main surface of the substrate and the carrier. During the arranging the substrate on the carrier, at least a part of the fixing agent formed over the at least one protrusion may be displaced into the space between the first main surface of the substrate and the carrier.

Abstract translation: 提供了一种连接衬底的方法，其中衬底可以包括第一主表面和与第一主表面相对的第二主表面。 该方法可以包括在基板的第一主表面上形成至少一个突起，在基板的第一主表面上并在该至少一个突起上方形成固定剂; 并将衬底布置在载体上。 所述至少一个突起可以接触所述载体的表面，并且可以被配置为将所述基板的所述第一主表面保持在与所述突起的高度相对应的所述载体的接触表面一定距离处，从而在所述第一 基板和载体的主表面。 在将衬底布置在载体上时，形成在至少一个突起上的固定剂的至少一部分可以位移到衬底的第一主表面和载体之间的空间中。

公开(公告)号：US20240088087A1

公开(公告)日：2024-03-14

申请号：US18509357

申请日：2023-11-15

Applicant: Infineon Technologies AG

Inventor： Alexander HEINRICH ,  Michael JUERSS ,  Konrad ROESL ,  Oliver EICHINGER ,  Kok Chai GOH ,  Tobias SCHMIDT

IPC: H01L23/00 ,  H01L23/482 ,  H01L23/495 ,  H01L29/43 ,  H01L29/45

CPC classification number: H01L24/32 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L29/43 ,  H01L29/45 ,  H01L2224/03438 ,  H01L2224/0345 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/08503 ,  H01L2224/2745 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29184 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/83191 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83464 ,  H01L2224/83469 ,  H01L2224/83815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01048 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/1776

Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

公开(公告)号：US20250100088A1

公开(公告)日：2025-03-27

申请号：US18774056

申请日：2024-07-16

Applicant: Infineon Technologies AG

Inventor： Alexander HEINRICH ,  Verena MUHR ,  Konrad RÖSL ,  Maximilian SIMMANN ,  Catharina WILLE

IPC: B23K35/36 ,  B23K35/02

Abstract: A solder material is provided. In one or more examples, the solder material may include metal solder particles, a carboxylic acid, and an alcohol selected from the group consisting of methanol, ethanol, propan-1-ol, propan-2-ol, 2-methyl-1-propanol, butan-1-ol, pentan-1-ol, 1,2-propanediol, 1,3-propanediol, and glycerol.

公开(公告)号：US20240258372A1

公开(公告)日：2024-08-01

申请号：US18518846

申请日：2023-11-24

Applicant: Infineon Technologies AG

Inventor： Sebastian POLSTER ,  Alexander HEINRICH ,  Martin Richard NIESSNER

IPC: H01L29/06 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L29/0657 ,  H01L21/78 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L29/1608 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/3201 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/8382 ,  H01L2924/10156 ,  H01L2924/10272

Abstract: An electronic component is disclosed. The electronic component comprises a semiconductor body, an active region in a central portion of the semiconductor body, and a stress release structure for releasing stress and being formed as a lateral edge portion of the semiconductor body. The lateral edge portion has a minimum thickness of not more than 40% of a maximum thickness of the semiconductor body.

公开(公告)号：US20200219848A1

公开(公告)日：2020-07-09

申请号：US16826340

申请日：2020-03-23

Applicant: Infineon Technologies AG

Inventor： Alexander HEINRICH

IPC: H01L25/065 ,  H01L23/482 ,  H01L23/00 ,  H01L23/13 ,  H01L25/00 ,  H01L23/495 ,  H01L21/683

Abstract: A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.