公开(公告)号：US20210167034A1

公开(公告)日：2021-06-03

申请号：US17149741

申请日：2021-01-15

Applicant: Infineon Technologies AG

Inventor： Manfred MENGEL ,  Alexander HEINRICH ,  Steffen ORSO ,  Thomas BEHRENS ,  Oliver EICHINGER ,  Lim FONG ,  Evelyn NAPETSCHNIG ,  Edmund RIEDL

IPC: H01L23/00 ,  B23K35/30 ,  B23K35/26 ,  B23K35/28 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/495 ,  B23K1/00

Abstract: A chip arrangement including: a chip including a chip back side; a substrate including a surface with a plating; and a zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy including, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc.

公开(公告)号：US20150102479A1

公开(公告)日：2015-04-16

申请号：US14501070

申请日：2014-09-30

Applicant: Infineon Technologies AG

Inventor： Edward FUERGUT ,  Manfred MENGEL

IPC: H01L23/31 ,  H01L21/52 ,  H01L23/367 ,  H01L21/56

CPC classification number: H01L23/3675 ,  H01L21/3105 ,  H01L21/4871 ,  H01L21/52 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/3737 ,  H01L23/4334 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.

Abstract translation: 一种用于制造电子半导体封装的方法，其中电子芯片（100）耦合到载体，所述电子芯片通过具有不连续性的封装结构至少部分地封装，并且所述载体被部分封装，并且在 不连续部分的至少一部分和与其邻接的与载体的暴露表面部分连接的体积被电绝缘热界面结构所覆盖，该电接口结构使载体的至少一部分相对于其周围环境电解耦。

公开(公告)号：US20160372399A1

公开(公告)日：2016-12-22

申请号：US15256640

申请日：2016-09-05

Applicant: Infineon Technologies AG

Inventor： Edward FUERGUT ,  Manfred MENGEL

IPC: H01L23/367 ,  H01L21/3105 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.

公开(公告)号：US20170323865A1

公开(公告)日：2017-11-09

申请号：US15659670

申请日：2017-07-26

Applicant: Infineon Technologies AG

Inventor： Manfred MENGEL ,  Alexander HEINRICH ,  Steffen ORSO ,  Thomas BEHRENS ,  Oliver EICHINGER ,  Lim FONG ,  Evelyn NAPETSCHNIG ,  Edmund RIEDL

IPC: H01L23/00 ,  B23K35/28 ,  B23K35/30 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/495 ,  B23K1/00 ,  C22C30/04 ,  B23K35/26

CPC classification number: H01L24/48 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/282 ,  B23K35/3013 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/05599 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/207

Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.