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18 条记录 (耗时 0.017 秒)

    Three level interconnect clip
    1.
    发明授权
    Three level interconnect clip 有权

    公开(公告)号：US12057376B2

    公开(公告)日：2024-08-06

    申请号：US17086976

    申请日：2020-11-02

    申请人： Infineon Technologies AG

    发明人： Azlina Kassim ,  Thai Kee Gan ,  Mark Pavier ,  Ke Yan Tean ,  Mohd Hasrul Zulkifli

    IPC分类号： H01L23/495 ,  H01L23/31

    CPC分类号： H01L23/49503 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49568

    摘要： An interconnect clip includes a die attach pad that comp includes rises a die attach surface at an inner side of the interconnect clip, a heat dissipation pad that includes a heat dissipation surface at an outer side of the interconnect clip, and a lead contact pad that includes a lead contact surface at an inner side of the interconnect clip or at an outer side of the interconnect clip. The outer side of the interconnect clip in the lead contact pad faces and is spaced apart from the inner side of the interconnect clip in the heat dissipation pad, and the inner side of the interconnect clip in the lead contact pad faces and is spaced apart from the outer side of the interconnect clip in the die attach pad.

    Semiconductor package including leads of different lengths
    3.
    发明授权
    Semiconductor package including leads of different lengths 有权

    公开(公告)号：US11417538B2

    公开(公告)日：2022-08-16

    申请号：US16882416

    申请日：2020-05-22

    申请人： Infineon Technologies AG

    发明人： Thai Kee Gan ,  Edmund Sales Cabatbat

    IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/673

    摘要： A semiconductor package includes a die pad, a die, a first lead, a plurality of second leads, and a mold material. The die is electrically coupled to the die pad. The first lead is electrically coupled to the die. The plurality of second leads are electrically coupled to the die. The plurality of second leads are adjacent to the first lead. The mold material encapsulates at least a portion of the die pad, the die, the first lead, and the plurality of second leads. Each of the plurality of second leads extends a farther distance from the mold material than the first lead.

    Three Level Interconnect Clip
    5.
    发明申请
    Three Level Interconnect Clip 有权

    公开(公告)号：US20220139811A1

    公开(公告)日：2022-05-05

    申请号：US17086976

    申请日：2020-11-02

    申请人： Infineon Technologies AG

    发明人： Azlina Kassim ,  Thai Kee Gan ,  Mark Pavier ,  Ke Yan Tean ,  Mohd Hasrul Zulkifli

    IPC分类号： H01L23/495 ,  H01L23/31

    摘要： An interconnect clip includes a die attach pad that comp includes rises a die attach surface at an inner side of the interconnect clip, a heat dissipation pad that includes a heat dissipation surface at an outer side of the interconnect clip, and a lead contact pad that includes a lead contact surface at an inner side of the interconnect clip or at an outer side of the interconnect clip. The outer side of the interconnect clip in the lead contact pad faces and is spaced apart from the inner side of the interconnect clip in the heat dissipation pad, and the inner side of the interconnect clip in the lead contact pad faces and is spaced apart from the outer side of the interconnect clip in the die attach pad.

    HIGH VOLTAGE SEMICONDUCTOR PACKAGE WITH PIN FIT LEADS
    7.
    发明申请
    HIGH VOLTAGE SEMICONDUCTOR PACKAGE WITH PIN FIT LEADS 有权

    公开(公告)号：US20220336401A1

    公开(公告)日：2022-10-20

    申请号：US17234964

    申请日：2021-04-20

    申请人： Infineon Technologies AG

    发明人： Edmund Sales Cabatbat ,  Thai Kee Gan ,  Kean Ming Koe ,  Ke Yan Tean

    IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/495 ,  H01L23/14 ,  H01L23/13

    摘要： A semiconductor package includes a die pad, a semiconductor die mounted on the die pad and comprising a first terminal facing away from the die pad and a second terminal facing and electrically connected to the die pad, an interconnect clip electrically connected to the first terminal, an encapsulant body of electrically insulating material that encapsulates the semiconductor die and the interconnect clip, and a first opening in the encapsulant body that exposes a surface of the interconnect clip, the encapsulant body comprises a lower surface, an upper surface opposite from the lower surface, and a first outer edge side extending between the lower surface and the upper surface, and the first opening is laterally offset from the first outer edge side.

    SEMICONDUCTOR PACKAGE HAVING A CHIP CARRIER WITH A PAD OFFSET FEATURE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE HAVING A CHIP CARRIER WITH A PAD OFFSET FEATURE 有权

    公开(公告)号：US20220102263A1

    公开(公告)日：2022-03-31

    申请号：US17459296

    申请日：2021-08-27

    申请人： Infineon Technologies AG

    发明人： Chee Yang Ng ,  Stefan Woetzel ,  Edward Fuergut ,  Thai Kee Gan ,  Chee Hong Lee ,  Jayaganasan Narayanasamy ,  Ralf Otremba

    IPC分类号： H01L23/498 ,  H01L23/00

    摘要： A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.

    Semiconductor package with space efficient lead and die pad design
    9.
    发明授权
    Semiconductor package with space efficient lead and die pad design 有权

    公开(公告)号：US11069600B2

    公开(公告)日：2021-07-20

    申请号：US16422163

    申请日：2019-05-24

    申请人： Infineon Technologies AG

    发明人： Ke Yan Tean ,  Thomas Bemmerl ,  Thai Kee Gan ,  Azlina Kassim

    IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

    摘要： A semiconductor package includes a die pad having a die attach surface, a rear surface opposite the die attach surface, and an outer edge side extending between the die attach surface and the rear surface, the outer edge side having a step-shaped profile, wherein an upper section of the die pad laterally overhangs past a lower section of the die pad, a semiconductor die mounted on the die attach surface and having a first electrical terminal on an upper surface of the semiconductor die, and a first conductive clip that directly electrically contacts the first electrical terminal and wraps around the outer edge side of the die pad such that a section of the first conductive clip is at least partially within an area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.