公开(公告)号：US12212649B2

公开(公告)日：2025-01-28

申请号：US18188629

申请日：2023-03-23

Applicant: Infineon Technologies AG

Inventor： George Efthivoulidis ,  Tony Gschier ,  Bernd Zimek ,  Peter Thurner ,  Thomas Santa

IPC: H04L7/00 ,  H04L7/033

Abstract: A radar monolithic microwave integrated circuit (MMIC) includes a trigger encoder configured to receive a clock signal comprising a plurality of clock pulses having a fixed amplitude and a trigger signal configured to indicate trigger events. The trigger encoder is configured to encode the trigger signal into the clock signal to generate a distributed clock signal by skipping at least one clock pulse of the plurality of clock pulses to indicate a trigger event. The radar MMIC is configured to output the distributed clock signal having the at least one clock pulse skipped to indicate the trigger event. The radar MMIC is configured to receive the distributed clock signal as a received distributed clock signal. The radar MMIC further includes a radar operation controller configured to detect the trigger event based on the received distributed clock signal and initiate a radar operation based on detecting the trigger event.

公开(公告)号：US11874682B1

公开(公告)日：2024-01-16

申请号：US18062312

申请日：2022-12-06

Applicant: Infineon Technologies AG

Inventor： Andrea Tollot ,  Thomas Santa ,  Andrea Bandiziol

IPC: G05F1/46 ,  G05F3/24 ,  H03F3/45 ,  G05F1/575

CPC classification number: G05F3/24 ,  G05F1/575 ,  H03F3/45475

Abstract: A circuit includes: a first load circuit and a second load circuit coupled in parallel between a first node and a reference voltage node, where the first load circuit and the second load circuit are configured to receive a first input signal and a second input signal, respectively; a first pass device and a first switch coupled in series between a voltage supply node and the first node; a second pass device and a second switch coupled in series between the voltage supply node and the first node; and an amplifier, where a first input terminal and a second input terminal of the amplifier are configured to be coupled to a reference input voltage and the first node, respectively, where an output terminal of the amplifier is coupled to a first control terminal of the first pass device and a second control terminal of the second pass device.

公开(公告)号：US09985639B2

公开(公告)日：2018-05-29

申请号：US14988745

申请日：2016-01-05

Applicant: Infineon Technologies AG

Inventor： Roberto Nonis ,  Peter Thurner ,  Thomas Santa

IPC: H03L7/00 ,  H03L7/24 ,  H03L7/08 ,  H04L7/00 ,  H03L7/093 ,  H03L1/02 ,  H03L7/099 ,  H03L7/10 ,  H03K9/08 ,  H04L7/033

CPC classification number: H03L7/24 ,  H03K9/08 ,  H03L1/022 ,  H03L7/08 ,  H03L7/081 ,  H03L7/093 ,  H03L7/099 ,  H03L7/10 ,  H03L7/113 ,  H03L7/183 ,  H03L2207/06 ,  H03L2207/50 ,  H04L7/00 ,  H04L7/033

Abstract: Representative implementations of devices and techniques provide non-linearity detection and mitigation for a phase interpolator of a controlled oscillator circuit, such as a PLL. A bit stream output of a phase detector of the oscillator circuit is segmented according to multiple phase positions of the phase interpolator, forming a bit stream for each of the multiple phase positions. Each bit stream of each phase position is analyzed, and phase position errors may be detected and mitigated based on the contents of the bit streams.

公开(公告)号：US09577622B2

公开(公告)日：2017-02-21

申请号：US14706874

申请日：2015-05-07

Applicant: Infineon Technologies AG

Inventor： Nicola Da Dalt ,  Roberto Nonis ,  Thomas Santa

IPC: H03H11/16 ,  H03K5/13 ,  H03H11/20 ,  H03K5/00

CPC classification number: H03K5/13 ,  H03H11/20 ,  H03K2005/00052

Abstract: Phase interpolators are provided where an adjustment current is added to currents from a plurality of switchable current sources, for example to reduce an integrated nonlinearity.

Abstract translation: 提供了相位插值器，其中调节电流被添加到来自多个可切换电流源的电流，例如以降低集成非线性。