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公开(公告)号：US08995600B1
公开(公告)日：2015-03-31
申请号：US14452360
申请日：2014-08-05
Applicant: INPHI Corporation
Inventor： Karthik S. Gopalakrishnan , Guojun Ren
CPC classification number: H04L7/0331 , H03K5/131 , H03K5/135 , H03L7/08 , H03L7/0814 , H04L27/04
Abstract: A phase interpolator (PI) is provided to adjust the phase of a clock such that the phase is aligned to an incoming data pattern from a data stream. The data can be captured from a device such as a flip-flop or the like. The present technique uses a PI (digital to phase) and a digital state machine in a feedback loop to set the correct digital code to the PI inputs to achieve an appropriate clock phase. Of course, there can be variations.
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公开(公告)号：US09806722B2
公开(公告)日：2017-10-31
申请号：US15235290
申请日：2016-08-12
Applicant: INPHI CORPORATION
Inventor： Guojun Ren , James Gorecki , Karthik S. Gopalakrishnan
CPC classification number: H03L7/0807 , H03L7/0805 , H03L7/0812 , H03L7/085
Abstract: The present invention is directed to signal processing system and electrical circuits. According to various embodiments, a DLL system includes a delay line provides multiple output signals associated with different clock phases. The delay line may be adjusted using a pair of bias voltages. A phase detector systems generates the bias voltages using the multiple output signals from the delay line. The multiple output signals include signals associated with the first phase, the last phase, and two adjacent phases. There are other embodiments as well.
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3.发明授权公开(公告)号：US09203605B2
公开(公告)日：2015-12-01
申请号：US14637308
申请日：2015-03-03
Applicant: INPHI CORPORATION
Inventor： Karthik S. Gopalakrishnan , Guojun Ren
CPC classification number: H04L7/0331 , H03K5/131 , H03K5/135 , H03L7/08 , H03L7/0814 , H04L27/04
Abstract: A phase interpolator (PI) is provided to adjust the phase of a clock such that the phase is aligned to an incoming data pattern from a data stream. The data can be captured from a device such as a flip-flop or the like. The present technique uses a PI (digital to phase) and a digital state machine in a feedback loop to set the correct digital code to the PI inputs to achieve an appropriate clock phase. Of course, there can be variations.
Abstract translation: 提供相位插值器（PI）以调整时钟的相位，使得该相位与来自数据流的输入数据模式对准。 可以从诸如触发器等的装置捕获数据。 本技术在反馈环路中使用PI（数字到相位）和数字状态机将正确的数字代码设置为PI输入以实现适当的时钟相位。 当然可以有变化。
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公开(公告)号：US09641313B1
公开(公告)日：2017-05-02
申请号：US14826051
申请日：2015-08-13
Applicant: INPHI CORPORATION
Inventor： Karthik S. Gopalakrishnan , Guojun Ren , Parmanand Mishra
CPC classification number: H03L7/0812 , H03K5/131 , H03K5/135 , H03K5/14 , H03K2005/00013 , H03K2005/00052 , H03K2005/00286 , H03L3/00 , H03L7/08 , H03L7/0807 , H03L7/0814 , H04L5/0053 , H04L7/002 , H04L7/0331 , H04L25/03273 , H04L27/04
Abstract: The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for regulating a voltage for a high speed serializer/deserializer (SerDes) device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications. In various embodiments, phase-interpolator is implemented in conjunction with a delay-lock loop (DLL) and an SR latch, where one or more outputs of the DLL is used by the SR latch. Additionally, such techniques can be used for a variety of applications such as network and/or computer storage systems, computer servers, hand held computing devices, portable computing devices, computer systems, network appliances and/or switches, routers, and gateways, and the like.
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公开(公告)号：US09438255B1
公开(公告)日：2016-09-06
申请号：US14815694
申请日：2015-07-31
Applicant: Inphi Corporation
Inventor： Guojun Ren , James Gorecki , Karthik S. Gopalakrishnan
CPC classification number: H03L7/0807 , H03L7/0805 , H03L7/0812 , H03L7/085
Abstract: The present invention is directed to signal processing system and electrical circuits. According to various embodiments, a DLL system includes a delay line provides multiple output signals associated with different clock phases. The delay line may be adjusted using a pair of bias voltages. A phase detector systems generates the bias voltages using the multiple output signals from the delay line. The multiple output signals include signals associated with the first phase, the last phase, and two adjacent phases. There are other embodiments as well.
Abstract translation: 本发明涉及信号处理系统和电路。 根据各种实施例，DLL系统包括延迟线，其提供与不同时钟相位相关联的多个输出信号。 可以使用一对偏置电压来调整延迟线。 相位检测器系统使用来自延迟线的多个输出信号产生偏置电压。 多个输出信号包括与第一阶段，最后阶段和两个相邻阶段相关联的信号。 还有其它实施例。
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Patent Agency Ranking
公开(公告)号：US08901977B1
公开(公告)日：2014-12-02
申请号：US14321602
申请日：2014-07-01
Applicant: Inphi Corporation
Inventor： Guojun Ren
CPC classification number: H03K5/14 , H02M3/07 , H03L7/0812 , H03L7/087 , H03L7/0896 , H03L7/0898
Abstract: The present invention is directed to signal processing system and electrical circuits. More specifically, embodiments of the present invention provide a DLL system that provides phase correction by determining a system offset based on phase differences among the delay lines. The offset is used as a part of a feedback loop to provide phase corrections for the delay lines. There are other embodiments as well.
Abstract translation: 本发明涉及信号处理系统和电路。 更具体地，本发明的实施例提供一种DLL系统，其通过基于延迟线之间的相位差确定系统偏移来提供相位校正。 偏移量用作反馈回路的一部分，为延迟线提供相位校正。 还有其它实施例。
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7.发明授权公开(公告)号：US08885691B1
公开(公告)日：2014-11-11
申请号：US13775041
申请日：2013-02-22
Applicant: Inphi Corporation
Inventor： Guojun Ren , Karthik S. Gopalakrishnan
Abstract: The voltage regulator device has a wide band amplifier having an input reference voltage, Vref and an input feedback voltage, Vfbk. The device has a source follower coupled to the wide band amplifier, the source follower coupled to an output of the wide band amplifier. The device has a VDD source, a regulator output, and a current source coupled to the source follower and the VDD source. The device has a low frequency path comprising a first transistor. The first transistor has a first gate, a first source, and a first drain. The first source is coupled to the VDD source. The first gate is coupled to a slow node, and the first drain is coupled to the regulator output. The low frequency path comprises a RC network, which has a capacitor, a resistor, and the slow node configured between the resistor and the capacitor. The device has a high frequency path comprising a second transistor. The second transistor has a second gate, a second source, and a second drain. The second source is coupled to the VDD source. The second gate is coupled to a fast node, and the second drain is coupled to the regulator output.
Abstract translation: 电压调节器装置具有宽带放大器，其具有输入参考电压Vref和输入反馈电压Vfbk。 该器件具有耦合到宽带放大器的源极跟随器，源极跟随器耦合到宽带放大器的输出。 器件具有VDD源，稳压器输出和耦合到源极跟随器和VDD源的电流源。 该器件具有包括第一晶体管的低频路径。 第一晶体管具有第一栅极，第一源极和第一漏极。 第一个源极耦合到VDD源。 第一栅极耦合到慢节点，第一漏极耦合到调节器输出端。 低频路径包括RC网络，其具有电容器，电阻器和配置在电阻器和电容器之间的慢节点。 该器件具有包括第二晶体管的高频路径。 第二晶体管具有第二栅极，第二源极和第二漏极。 第二个源极耦合到VDD源。 第二栅极耦合到快节点，第二漏极耦合到调节器输出。
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公开(公告)号：US09806686B1
公开(公告)日：2017-10-31
申请号：US15272828
申请日：2016-09-22
Applicant: INPHI CORPORATION
Inventor： Guojun Ren
CPC classification number: H03G1/0029 , H03F3/45179 , H03F3/45197 , H03F2203/45154 , H03F2203/45454 , H03F2203/45492 , H03F2203/45696 , H03F2203/45702 , H03G1/0023 , H03G1/007
Abstract: The present invention is directed to electrical circuits and techniques thereof. More specifically, an embodiment of the present invention provides a variable gain amplifier that includes a first transistor and a second transistor whose gate terminals are coupled to a first input terminal. A first drain terminal of the first transistor and a first source terminal of the second transistor is coupled to a voltage gain control switch. There are other embodiments as well.
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公开(公告)号：US09780797B2
公开(公告)日：2017-10-03
申请号：US15464750
申请日：2017-03-21
Applicant: INPHI CORPORATION
Inventor： Karthik S. Gopalakrishnan , Guojun Ren , Parmanand Mishra
CPC classification number: H03L7/0812 , H03K5/131 , H03K5/135 , H03K5/14 , H03K2005/00013 , H03K2005/00052 , H03K2005/00286 , H03L3/00 , H03L7/08 , H03L7/0807 , H03L7/0814 , H04L5/0053 , H04L7/002 , H04L7/0331 , H04L25/03273 , H04L27/04
Abstract: The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for regulating a voltage for a high speed serializer/deserializer (SerDes) device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications. In various embodiments, phase-interpolator is implemented in conjunction with a delay-lock loop (DLL) and an SR latch, where one or more outputs of the DLL is used by the SR latch. Additionally, such techniques can be used for a variety of applications such as network and/or computer storage systems, computer servers, hand held computing devices, portable computing devices, computer systems, network appliances and/or switches, routers, and gateways, and the like.
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公开(公告)号：US09041445B1
公开(公告)日：2015-05-26
申请号：US14519014
申请日：2014-10-20
Applicant: INPHI CORPORATION
Inventor： Guojun Ren
CPC classification number: H03K5/14 , H02M3/07 , H03L7/0812 , H03L7/087 , H03L7/0896 , H03L7/0898
Abstract: The present invention is directed to signal processing system and electrical circuits. More specifically, embodiments of the present invention provide a DLL system that provides phase correction by determining a system offset based on phase differences among the delay lines. The offset is used as a part of a feedback loop to provide phase corrections for the delay lines. There are other embodiments as well.
Abstract translation: 本发明涉及信号处理系统和电路。 更具体地，本发明的实施例提供一种DLL系统，其通过基于延迟线之间的相位差确定系统偏移来提供相位校正。 偏移量用作反馈回路的一部分，为延迟线提供相位校正。 还有其它实施例。
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