MULTI-LAYER PACKAGE
    1.
    发明申请
    MULTI-LAYER PACKAGE 审中-公开

    公开(公告)号:US20170207170A1

    公开(公告)日:2017-07-20

    申请号:US15106761

    申请日:2015-07-22

    Abstract: Embodiments herein relate to a system in package (SiP). The SiP may have a first layer of one or more first functional components with respective first active sides and first inactive sides opposite the first active sides. The SiP may further include a second layer of one or more second functional components with respective second active sides and second inactive sides opposite the second active sides. In embodiments, one or more of the first active sides are facing and electrically coupled with one or more of the second active sides through a through-mold via or a through-silicon via.

    SINGLE LAYER LOW COST WAFER LEVEL PACKAGING FOR SFF SIP

    公开(公告)号:US20180301435A1

    公开(公告)日:2018-10-18

    申请号:US16015052

    申请日:2018-06-21

    Abstract: In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board.

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