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公开(公告)号：US10281975B2
公开(公告)日：2019-05-07
申请号：US15190417
申请日：2016-06-23
Applicant: Intel Corporation
Inventor： Efraim Rotem , Doron Rajwan , Eliezer Weissmann , Nir Rosenzweig , Eric Distefano , Ishmael F. Santos , James G. Hermerding, II
IPC: G06F1/00 , G06F1/26 , G06F1/32 , G06F1/3296 , G06F1/3228 , G06F9/30
Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
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公开(公告)号：US09710030B2
公开(公告)日：2017-07-18
申请号：US14570945
申请日：2014-12-15
Applicant: Intel Corporation
Inventor： Ketan R. Shah , Tawfik M. Rahal-Arabi , Eric Distefano , James G. Hermerding, II
CPC classification number: G06F1/206 , G06F1/26 , G06F1/3203 , Y02D10/16
Abstract: Embodiments of an apparatus, system and method are described for configurable processor thermal management. An apparatus may comprise, for example, a processor arranged to operate in a plurality of thermal modes comprising a thermal limit down mode, a normal thermal limit mode and a thermal limit up mode, and thermal management logic operative to select a thermal mode based on one or more properties of the apparatus. Other embodiments are described and claimed.
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公开(公告)号：US10990161B2
公开(公告)日：2021-04-27
申请号：US16382311
申请日：2019-04-12
Applicant: Intel Corporation
Inventor： Efraim Rotem , Doron Rajwan , Eliezer Weissmann , Nir Rosenzweig , Eric Distefano , Ishmael F. Santos , James G. Hermerding, II
IPC: G06F1/00 , G06F1/3296 , G06F1/3228 , G06F9/30 , G06F1/324
Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
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公开(公告)号：US09898067B2
公开(公告)日：2018-02-20
申请号：US15089350
申请日：2016-04-01
Applicant: Intel Corporation
Inventor： Eric Distefano , Guy M. Therien , Vasudevan Srinivasan , Tawfik M. Rahal-Arabi , Venkatesh Ramani , Ryan D. Wells , Stephen H. Gunther , Jeremy J. Shrall , James G. Hermerding, II
CPC classification number: G06F1/3234 , G06F1/206 , G06F1/26 , Y02D10/16
Abstract: A technique to change a thermal design power (TDP) value. In one embodiment, one or more environmental or user-driven changes may cause a processor's TDP value to be changed. Furthermore, in some embodiments a change in TDP may alter a turbo mode target frequency.
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公开(公告)号：US09898066B2
公开(公告)日：2018-02-20
申请号：US14645330
申请日：2015-03-11
Applicant: Intel Corporation
Inventor： Eric Distefano , Guy M. Therien , Vasudevan Srinivasan , Tawfik Rahal-Arabi , Venkatesh Ramani , Ryan D. Wells , Stephen H. Gunther , Jeremy Shrall , Hames Hermerding, II
CPC classification number: G06F1/3234 , G06F1/206 , G06F1/26 , Y02D10/16
Abstract: A technique to change a thermal design power (TDP) value. In one embodiment, one or more environmental or user-driven changes may cause a processor's TDP value to be changed. Furthermore, in some embodiments a change in TDP may alter a turbo mode target frequency.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20150377955A1
公开(公告)日：2015-12-31
申请号：US14319197
申请日：2014-06-30
Applicant: Intel Corporation
Inventor： Dorit Shapira , Krishnakanth V. Sistla , Efraim Rotem , Eric Distefano , James G. Hermerding, II , Esfir Natanzon
CPC classification number: G06F11/3024 , G01R31/2856 , G06F1/324 , G06F1/3296 , G06F11/3058 , G06F11/3409 , G06F2201/81 , Y02D10/126 , Y02D10/172
Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information from a user or manufacturer and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.
Abstract translation: 一种用户可配置可靠性控制回路的装置和方法。 例如，处理器的一个实施例包括：可靠性计量器，用于基于测量的处理器操作条件跟踪处理器的部件上的累积应力; 以及控制器，用于从用户或制造商接收压力限制信息，并且根据累积的应力和应力限制信息响应地在处理器上指定一组N个操作限制; 以及性能选择逻辑，用于基于由控制器指定的N个操作限制来输出处理器的一个或多个实际操作条件。
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公开(公告)号：US20210349522A1
公开(公告)日：2021-11-11
申请号：US17215104
申请日：2021-03-29
Applicant: Intel Corporation
Inventor： Efraim Rotem , Doron Rajwan , Eliezer Weissmann , Nir Rosenzweig , Eric Distefano , Ishmael F. Santos , James G. Hermerding, II
IPC: G06F1/3296 , G06F1/3228 , G06F9/30
Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
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公开(公告)号：US20190235618A1
公开(公告)日：2019-08-01
申请号：US16382311
申请日：2019-04-12
Applicant: Intel Corporation
Inventor： Efraim Rotem , Doron Rajwan , Eliezer Weissmann , Nir Rosenzweig , Eric Distefano , Ishmael F. Santos , James G. Hermerding, II
IPC: G06F1/3296 , G06F1/3228 , G06F9/30
CPC classification number: G06F1/3296 , G06F1/3228 , G06F1/324 , G06F9/30101 , G06F9/30145
Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
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公开(公告)号：US10289514B2
公开(公告)日：2019-05-14
申请号：US14319197
申请日：2014-06-30
Applicant: Intel Corporation
Inventor： Dorit Shapira , Krishnakanth V. Sistla , Efraim Rotem , Eric Distefano , James G. Hermerding, II , Esfir Natanzon
IPC: G06F11/30 , G06F11/34 , G06F1/324 , G06F1/3296 , G01R31/28
Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.
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公开(公告)号：US20150100799A1
公开(公告)日：2015-04-09
申请号：US14570945
申请日：2014-12-15
Applicant: Intel Corporation
Inventor： Ketan R. Shah , Tawfik M. Rahal-Arabi , Eric Distefano , James G. Hermerding, II
CPC classification number: G06F1/206 , G06F1/26 , G06F1/3203 , Y02D10/16
Abstract: Embodiments of an apparatus, system and method are described for configurable processor thermal management. An apparatus may comprise, for example, a processor arranged to operate in a plurality of thermal modes comprising a thermal limit down mode, a normal thermal limit mode and a thermal limit up mode, and thermal management logic operative to select a thermal mode based on one or more properties of the apparatus. Other embodiments are described and claimed.
Abstract translation: 描述了可配置的处理器热管理的装置，系统和方法的实施例。 例如，设备可以包括处理器，其被布置成以包括热限制模式，正常热限制模式和热限制模式的多个热模式操作，以及热管理逻辑，其可操作以基于 设备的一个或多个属性。 描述和要求保护其他实施例。
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