公开(公告)号：US20150364425A1

公开(公告)日：2015-12-17

申请号：US14836828

申请日：2015-08-26

申请人： Intel Corporation

发明人： Kevin J. Lee ,  Mark T. BOHR ,  Andrew W. YEOH ,  Christopher M. PELTO ,  Hiten KOTHARI ,  Seshu V. SATTIRAJU ,  Hang-Shing MA

IPC分类号： H01L23/538 ,  H01L23/29 ,  H01L23/528 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/5384 ,  H01L21/6835 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5286 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/17 ,  H01L2221/6835 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17106 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/186 ,  H01L2924/381 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/05552

摘要： A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.

摘要翻译： 描述了3D互连结构和制造方法，其中使用双镶嵌型工艺流程形成穿硅通孔（TSV）和金属再分布层（RDL）。 氮化硅或碳化硅钝化层可以设置在减薄的器件晶片背面和RDL之间，以在工艺流程期间提供气密屏障和蚀刻停止层。