公开(公告)号：US20190237391A1

公开(公告)日：2019-08-01

申请号：US16329170

申请日：2016-10-27

申请人： Intel Corporation

发明人： Seshu V. SATTIRAJU ,  Krishna Prakash GANESAN ,  Ashish BHATIA ,  Vinay SRIRAM ,  John MUIRHEAD ,  Hiten KOTHARI ,  Aloysius A. GUNAWAN ,  Lavanya ARYASOMAYAJULA ,  Shravan GOWRISHANKAR ,  Sriram PATTABHIRAMAN ,  Sudipto GUHA

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L25/18 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/822

CPC分类号： H01L23/481 ,  H01L21/48 ,  H01L21/76876 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/00 ,  H01L23/48 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/18 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05657 ,  H01L2224/06153 ,  H01L2224/06155 ,  H01L2224/06181 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/335 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/014

摘要： A stacked-chip assembly including a plurality of IC chips or die that are stacked, and electrically coupled by solder bonds. In accordance with some embodiments described further below, the solder bonds are to contact a back-side land that includes a diffusion barrier to reduce intermetallic formation and/or other solder-induced reliability issues. The back-side land may include an electrolytic nickel (Ni) barrier layer separating solder from a back-side redistribution layer trace. This electrolytic Ni may be of high purity, which at least in part, may enable the backside metallization stack to be of minimal thickness while still functioning as a diffusion barrier. In some embodiments, the back-side land composition and architecture is distinct from a front-side land composition and/or architecture.

公开(公告)号：US20210057348A1

公开(公告)日：2021-02-25

申请号：US16650292

申请日：2017-12-19

申请人： Intel Corporation

发明人： Ehren HWANG ,  Christopher M. PELTO ,  Seshu V. SATTIRAJU ,  Shravan GOWRISHANKAR ,  Zachary A. ZELL ,  Digvijay A. RAORANE

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

摘要： Disclosed are barrier materials between bumps and pads, and related devices and methods. A semiconductor device includes an interconnect, a top material, a pad on the interconnect and at least a portion of the top material, a bump on the pad, and a barrier material between the pad and the bump. The top material defines a via therethrough to the interconnect. The pad includes electrically conductive material. The bump includes electrically conductive material. The bump is configured to electrically connect the interconnect to another device. The barrier material is between the pad and the bump. The barrier material includes a conductive material that is resistant to electromigration, intermetallic compound reaction, or both electromigration and intermetallic compound reaction.

公开(公告)号：US20150364425A1

公开(公告)日：2015-12-17

申请号：US14836828

申请日：2015-08-26

申请人： Intel Corporation

发明人： Kevin J. Lee ,  Mark T. BOHR ,  Andrew W. YEOH ,  Christopher M. PELTO ,  Hiten KOTHARI ,  Seshu V. SATTIRAJU ,  Hang-Shing MA

IPC分类号： H01L23/538 ,  H01L23/29 ,  H01L23/528 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/5384 ,  H01L21/6835 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5286 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/17 ,  H01L2221/6835 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17106 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/186 ,  H01L2924/381 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/05552

摘要： A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.

摘要翻译： 描述了3D互连结构和制造方法，其中使用双镶嵌型工艺流程形成穿硅通孔（TSV）和金属再分布层（RDL）。 氮化硅或碳化硅钝化层可以设置在减薄的器件晶片背面和RDL之间，以在工艺流程期间提供气密屏障和蚀刻停止层。