公开(公告)号：US20020089833A1

公开(公告)日：2002-07-11

申请号：US10076893

申请日：2002-02-14

Applicant: Intel Corporation

Inventor： P.R. Patel ,  Yuan-Liang Li ,  David G. Figueroa ,  Shamala Chickamenahalli ,  Huong T. Do

IPC: H05K007/02 ,  H05K007/06

CPC classification number: H05K1/141 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15192 ,  H05K1/0262 ,  H05K3/368 ,  H05K7/1092 ,  H05K2201/049 ,  H05K2201/10196 ,  H05K2201/10325 ,  H05K2201/10689 ,  H05K2201/10704 ,  H01L2224/0401

Abstract: An interposer includes two separate sets of pins, and inserts into two sockets on a printed circuit board. One set of pins supplies power to a step down converter (SDC) mounted on the interposer. The second set of pins provide inputs and outputs to an integrated circuit mounted on the interposer. One or more conductive traces in or on the interposer electrically connect an output of the SDC to an input of the integrated circuit, thus supplying regulated power to the integrated circuit through the interposer. The SDC and integrated circuit can be directly mounted on the interposer, or either or both can be mounted on packages that connect to the interposer. The SDC and integrated circuit can be flip chips or can be connected to the interposer or package using wirebonds. The packages can be pinned or connectable by solder bumps.

公开(公告)号：US20020075630A1

公开(公告)日：2002-06-20

申请号：US09741302

申请日：2000-12-19

Applicant: Intel Corporation

Inventor： David G. Figueroa ,  Huong T. Do ,  Jorge Pedro Rodriguez ,  Michael Walk

IPC: H01G002/20

CPC classification number: H01G2/065 ,  H01L2924/15311

Abstract: A capacitor (FIGS. 6-9) includes one or more extended surface lands (604, 704, 804, 904, FIGS. 6-9). In one embodiment, each extended surface land is a land on a top or bottom surface of the capacitor, having a land length that is equal to at least 30% of the width (614, FIG. 6) of the capacitor or 20% of the length (914, FIG. 9) of the capacitor. When embedded within an integrated circuit package (1102, FIG. 11), two or more vias (1112) can be electrically connected to the extended surface lands (1108).

Abstract translation: 电容器（图6-9）包括一个或多个延伸的表面焊盘（604,704,804,904，图6-9）。 在一个实施例中，每个延伸的表面焊盘是电容器的顶部或底部表面上的焊盘，其具有等于电容器的宽度（614，图6）的至少30％的平台长度或20％ 电容器的长度（914，图9）。 当嵌入在集成电路封装（1102，图11）中时，两个或更多个通孔（1112）可以电连接到扩展表面焊盘（1108）。

公开(公告)号：US20020134581A1

公开(公告)日：2002-09-26

申请号：US10155628

申请日：2002-05-24

Applicant: Intel Corporation

Inventor： David G. Figueroa ,  Yuan-Liang Li ,  Huong T. Do

IPC: H05K001/16 ,  H01G004/38 ,  H01L029/00

CPC classification number: H01L23/642 ,  H01L2924/0002 ,  H01L2924/15312 ,  H01L2924/19105 ,  H05K1/141 ,  H05K1/162 ,  Y10T29/435 ,  H01L2924/00

Abstract: A hybrid capacitor associated with an integrated circuit package provides multiple levels of excess, off-chip capacitance to die loads. The hybrid capacitor includes a low inductance, parallel plate capacitor embedded within the package, and electrically connected to a second source of off-chip capacitance. The parallel plate capacitor is disposed underneath a die, and includes a top conductive layer, a bottom conductive layer, and a thin dielectric layer that electrically isolates the top and bottom layers. The second source of off-chip capacitance is a set of self-aligned via capacitors, and/or one or more discrete capacitors, and/or an additional parallel plate capacitor. Each of the self-aligned via capacitors is embedded within the package, and has an inner conductor and an outer conductor. The inner conductor is electrically connected to either the top or bottom conductive layer, and the outer conductor is electrically connected to the other conductive layer. The discrete capacitors are electrically connected to contacts from the conductive layers to the surface of the package. During operation, one of the conductive layers of the low inductance parallel plate capacitor provides a ground plane, while the other conductive layer provides a power plane.

Abstract translation: 与集成电路封装相关联的混合电容为裸片负载提供多级多余的片外电容。 混合电容器包括嵌入在封装内的低电感并联板电容器，并且电连接到片外电容的第二源极。 平行板电容器设置在管芯下方，并且包括顶部导电层，底部导电层和电绝缘顶层和底层的薄介电层。 片外电容的第二个源是一组自对准通孔电容器和/或一个或多个分立电容器和/或附加的平行板电容器。 每个自对准通孔电容器嵌入在封装内，并具有内部导体和外部导体。 内部导体电连接到顶部或底部导电层，并且外部导体电连接到另一个导电层。 分立电容器电连接到从导电层到封装表面的触点。 在操作期间，低电感平行板电容器的导电层之一提供接地平面，而另一导电层提供电源平面。

公开(公告)号：US20020085334A1

公开(公告)日：2002-07-04

申请号：US09751612

申请日：2000-12-29

Applicant: Intel Corporation

Inventor： David G. Figueroa ,  Kishore K. Chakravorty ,  Huong T. Do ,  Larry Eugene Mosley ,  Jorge Pedro Rodriguez ,  Ken Brown

IPC: H01G004/30

CPC classification number: H01G4/30 ,  H01L23/642 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/0298 ,  H05K1/162 ,  H01L2224/0401

Abstract: A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, FIGS. 3, 12, 13), which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, FIGS. 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, FIGS. 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tiers (1310, 1312, FIG. 13) are located in a center region (1404, FIG. 14) of the capacitor, and one or more other tiers (1380, FIG. 13) are located in a peripheral region (1408, FIG. 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, FIG. 13) of patterned conductive material. The capacitors of the various embodiments can be used as discrete devices, which are mountable on or embeddable within a housing (e.g., a package, interposer, socket or PC board), or they can be integrally fabricated within the housing.

Abstract translation: 电容器包括多层（302,304,306,1210,1212,1310,1312,1380，图3,12,13），其以不同的电感值向负载提供电容。 每个层包括被介电材料层隔开的图案化导电材料的多层（311-325,1220,1222,1320,1322,1382，图3,12,13）。 在一个实施例中，层是沿垂直方向堆叠的，并且通过延伸穿过一些或所有层的通孔（330,332,334,1230,1232，图3,12）电连接。 在另一个实施例中，一个或多个层（1310,1312，图13）位于电容器的中心区域（1404，图14）中，并且一个或多个其他层（图13中的1380）位于 电容器的外围区域（1408，图14）。 在该实施例中，中心层和外围层通过图案化导电材料的一个或多个附加层（1370，图13）电连接。 各种实施例的电容器可以用作可安装在壳体（例如，封装，插入件，插座或PC板）中或嵌入其中的分立器件，或者它们可以一体地制造在壳体内。