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    NONVOLATILE MEMORY MODULE
    1.
    发明申请
    NONVOLATILE MEMORY MODULE 审中-公开
    非易失性存储器模块

    公开(公告)号：US20160093377A1

    公开(公告)日：2016-03-31

    申请号：US14498480

    申请日：2014-09-26

    Applicant: Intel Corporation

    Inventor： Mani Prakash ,  Edward L. Payton ,  John K. Grooms ,  Dimitrios Ziakas ,  Mohammed Arafa ,  Raj K. Ramanujan ,  Dong Wang

    IPC: G11C14/00 ,  G11C7/10 ,  G11C11/406

    CPC classification number: G11C14/0018 ,  G11C5/04 ,  G11C7/1072 ,  G11C11/40615

    Abstract: Memory modules, controllers, and electronic devices comprising memory modules are described. In one embodiment, a memory module comprises a nonvolatile memory and an interface to a volatile memory bus, at least one input power rail to receive power from a host platform, and a controller comprising logic, at least partially including hardware logic, to convert the power from the input power rail from an input voltage to at least one output voltage, different from the input voltage. Other embodiments are also disclosed and claimed.

    Abstract translation: 描述了包括存储器模块的存储器模块，控制器和电子设备。 在一个实施例中，存储器模块包括非易失性存储器和到易失性存储器总线的接口，至少一个用于从主机平台接收电力的输入电源轨，以及控制器，其包括至少部分地包括硬件逻辑的逻辑，以将 从输入电源轨从输入电压到不同于输入电压的至少一个输出电压的电力。 还公开并要求保护其他实施例。

    Techniques for use of a multipurpose latch
    3.
    发明授权
    Techniques for use of a multipurpose latch 有权

    公开(公告)号：US11272632B2

    公开(公告)日：2022-03-08

    申请号：US16832399

    申请日：2020-03-27

    Applicant: Intel Corporation

    Inventor： Jorge U. Martinez Araiza ,  Paul J. Gwin ,  John K. Grooms

    IPC: H05K7/14

    Abstract: Examples may include techniques for use of a latch to secure a device inserted in a host computing system. The latch including a housing having holes or ports and an active contacts pad to receive external communication or control links routed through the holes or ports and to further route the communication or control links to circuitry at the device. The latch also including a securing pin attached to a lever to secure the device to the host computing system when the lever is engaged.

    Warm boot attack mitigations for non-volatile memory modules
    4.
    发明授权
    Warm boot attack mitigations for non-volatile memory modules 有权

    公开(公告)号：US11354415B2

    公开(公告)日：2022-06-07

    申请号：US16457928

    申请日：2019-06-29

    Applicant: Intel Corporation

    Inventor： Anna Trikalinou ,  Daniel S. Lake ,  Sham M. Datta ,  Asher M. Altman ,  John K. Grooms

    IPC: H04N7/16 ,  G06F7/04 ,  G06F21/57 ,  G06F12/14 ,  G06F21/79

    Abstract: Technologies disclosed herein provide mitigations against warm boot attacks on memory modules. For instance, in one embodiment, a non-volatile dual in-line memory module (NVDIMM) in a host computing system may detect a transition from a low-power state to a full-power state, receive a nonce value from a processor of the host computing system after the transition, verify the nonce value, and allow access to data stored on the NVDIMM based on successful verification of the nonce value. In another embodiment, an NVDIMM may be locked in response to detecting a transition from a high-power state to a low-power state in a host computing system. After a transition from the low-power state to the full-power state, the NVDIMM may obtain one or more passphrases, verify the one or more passphrases, and allow access to data stored on the NVDIMM based on successful verification of the one or more passphrases.

    WARM BOOT ATTACK MITIGATIONS FOR NON-VOLATILE MEMORY MODULES
    5.
    发明申请
    WARM BOOT ATTACK MITIGATIONS FOR NON-VOLATILE MEMORY MODULES 审中-公开

    公开(公告)号：US20190325142A1

    公开(公告)日：2019-10-24

    申请号：US16457928

    申请日：2019-06-29

    Applicant: Intel Corporation

    Inventor： Anna Trikalinou ,  Daniel S. Lake ,  Sham M. Datta ,  Asher M. Altman ,  John K. Grooms

    IPC: G06F21/57 ,  G06F12/14 ,  G06F21/79

    Abstract: Technologies disclosed herein provide mitigations against warm boot attacks on memory modules. For instance, in one embodiment, a non-volatile dual in-line memory module (NVDIMM) in a host computing system may detect a transition from a low-power state to a full-power state, receive a nonce value from a processor of the host computing system after the transition, verify the nonce value, and allow access to data stored on the NVDIMM based on successful verification of the nonce value. In another embodiment, an NVDIMM may be locked in response to detecting a transition from a high-power state to a low-power state in a host computing system. After a transition from the low-power state to the full-power state, the NVDIMM may obtain one or more passphrases, verify the one or more passphrases, and allow access to data stored on the NVDIMM based on successful verification of the one or more passphrases.

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