公开(公告)号：US20240312819A1

公开(公告)日：2024-09-19

申请号：US18185427

申请日：2023-03-17

Applicant: Intel Corporation

Inventor： Hong Seung YEON ,  Mariano PHIELIPP ,  Yi LI ,  Minglu LIU ,  Robin McREE ,  Yosuke KANAOKA ,  Gang DUAN

IPC: H01L21/68 ,  H01L21/67

CPC classification number: H01L21/68 ,  H01L21/67259

Abstract: A method for real-time offset adjustment of a semiconductor die placement comprising: obtaining or receiving operational parameters of a die mounting tool in real-time, wherein the die mounting tool is configured for placing the semiconductor die on a panel; predicting an offset adjustment of the semiconductor die placement based on the operational parameters; and determining semiconductor die placement coordinates based on an original die placement and the offset adjustment.

公开(公告)号：US20240213164A1

公开(公告)日：2024-06-27

申请号：US18089483

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Gang DUAN ,  Liang HE ,  Ziyin LIN ,  Elizabeth NOFEN ,  Yiqun BAI ,  Jonathan ATKINS ,  Jesus S. NIETO PESCADOR ,  Srinivas V. PIETAMBARAM ,  Kristof DARMAWIKARTA

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5381 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/14 ,  H01L2224/16104

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, and an opening in the package substrate. In an embodiment, a plurality of first pads are provided at a bottom of the opening, and a bridge die is in the opening. In an embodiment, the bridge die comprises a plurality of second pads that are coupled to the first pads by solder. In an embodiment, a non-conductive film (NCF) is around the solder between the first pads and the second pads.

公开(公告)号：US20240186280A1

公开(公告)日：2024-06-06

申请号：US18060596

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Andrey GUNAWAN ,  Gang DUAN ,  Edvin CETEGEN ,  Yuting WANG ,  Mine KAYA ,  Kartik SRINIVASAN ,  Mihir OKA ,  Anurag TRIPATHI

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/7598 ,  H01L2224/75985 ,  H01L2224/81093 ,  H01L2224/81097 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/95093 ,  H01L2224/97 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/3841

Abstract: The present disclosure is directed to an apparatus having a bond head configured to heat and compress a semiconductor package assembly, and a bonding stage configured to hold the semiconductor package assembly, wherein the bonding stage comprises a ceramic material including silicon and either magnesium or indium.

公开(公告)号：US20240178151A1

公开(公告)日：2024-05-30

申请号：US18071901

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Alexander AGUINAGA ,  Gang DUAN ,  Jung Kyu HAN ,  Yosuke KANAOKA ,  Yi LI ,  Robin MCREE ,  Hong Seung YEON

IPC: H01L23/544 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/544 ,  H01L23/15 ,  H01L23/49816

Abstract: Embodiments disclosed herein include a package architecture. In an embodiment, the package architecture comprises a first substrate with a first fiducial mark on a surface of the first substrate. In an embodiment, the package architecture further comprises a second substrate over the first substrate, where the second substrate comprises glass and a second fiducial mark on the second substrate, and where a footprint of the second fiducial mark at least partially overlaps a footprint of the first fiducial mark.

公开(公告)号：US20240078702A1

公开(公告)日：2024-03-07

申请号：US17902907

申请日：2022-09-05

Applicant: Intel Corporation

Inventor： Yi LI ,  Hong Seung YEON ,  Nicholas HAEHN ,  Wei LI ,  Raquel DE SOUZA BORGES FERREIRA ,  Minglu LIU ,  Robin McREE ,  Yosuke KANAOKA ,  Gang DUAN ,  Arnab ROY

IPC: G06T7/73 ,  H01L21/68 ,  H01L23/544

CPC classification number: G06T7/74 ,  H01L21/681 ,  H01L23/544 ,  G06T2207/20081 ,  G06T2207/30204 ,  H01L2223/54426

Abstract: A method for recognizing a reference point associated with a fiducial marker including the steps of: obtaining or receiving image data of the fiducial marker; determining the degree of which the image data of the fiducial marker is aligned with one or more reference images; of which if the degree of alignment is determined to be less than an acceptable threshold predicting a set of coordinates of the reference point associated with the fiducial marker; incorporating the set of coordinates with the image data to form a modified image data; and determining the degree of which the modified image data of the fiducial marker is aligned with one or more reference images.

公开(公告)号：US20240186281A1

公开(公告)日：2024-06-06

申请号：US18060617

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Andrey GUNAWAN ,  Gang DUAN

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L24/95 ,  H01L25/50 ,  H01L25/0655

Abstract: The present disclosure is directed to a thermocompression bonding tool having a bond head with a surface for compression and heating and a sensor, a stage for compression and heating, and a controller, and a method for its use for chip gap height and alignment control. For chip gap height and alignment control, the controller is provided with a recipe displacement and temperature profile and measured offsets.

公开(公告)号：US20240186279A1

公开(公告)日：2024-06-06

申请号：US18060577

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Yosuke KANAOKA ,  Jung Kyu HAN ,  Gang DUAN ,  Ziyin LIN

IPC: H01L23/00 ,  B32B37/12

CPC classification number: H01L24/75 ,  B32B37/12 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/7531 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83874 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/069 ,  H01L2924/0715

Abstract: The present disclosure relates to a system. The system may include a stage configured to support a substrate. The system may also include a bondhead configured to press a device against the substrate. The system may further include a light source configured to emit UV light towards the stage.

公开(公告)号：US20240186251A1

公开(公告)日：2024-06-06

申请号：US18075360

申请日：2022-12-05

Applicant: Intel Corporation

Inventor： Minglu LIU ,  YANG WU ,  Yuting WANG ,  Lawrence ROSS ,  Mine KAYA ,  Gang DUAN ,  Edvin CETEGEN ,  Alexander AGUINAGA

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/13 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/13 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/81203 ,  H01L2924/351

Abstract: Embodiments disclosed herein include package architectures. In an embodiment, the package architecture comprises a package substrate, a first bridge in the package substrate, where the first bridge includes conductive routing, and a second bridge in the package substrate. In an embodiment, the package architecture further comprises a third bridge in the package substrate, where the second bridge and the third bridge are positioned symmetrically about the first bridge.