公开(公告)号：US20240312819A1

公开(公告)日：2024-09-19

申请号：US18185427

申请日：2023-03-17

Applicant: Intel Corporation

Inventor： Hong Seung YEON ,  Mariano PHIELIPP ,  Yi LI ,  Minglu LIU ,  Robin McREE ,  Yosuke KANAOKA ,  Gang DUAN

IPC: H01L21/68 ,  H01L21/67

CPC classification number: H01L21/68 ,  H01L21/67259

Abstract: A method for real-time offset adjustment of a semiconductor die placement comprising: obtaining or receiving operational parameters of a die mounting tool in real-time, wherein the die mounting tool is configured for placing the semiconductor die on a panel; predicting an offset adjustment of the semiconductor die placement based on the operational parameters; and determining semiconductor die placement coordinates based on an original die placement and the offset adjustment.

公开(公告)号：US20150194401A1

公开(公告)日：2015-07-09

申请号：US14658089

申请日：2015-03-13

Applicant: INTEL CORPORATION

Inventor： Rajasekaran SWAMINATHAN ,  Leonel R. ARANA ,  Yoshihiro TOMITA ,  Yosuke KANAOKA

IPC: H01L23/00 ,  H01L25/10

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11849 ,  H01L2224/16012 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2203/043 ,  H05K2203/083 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

Abstract translation: 描述形成微电子封装结构的方法。 这些方法可以包括在衬底上形成包含牺牲聚合物的焊膏，将焊膏固化在焊料的回流温度以下，以在导电焊盘上形成固体复合混合凸块，在固体复合混合凸块周围形成模塑料， 并且回流混合凸块，其中牺牲聚合物基本分解。

公开(公告)号：US20240186279A1

公开(公告)日：2024-06-06

申请号：US18060577

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Yosuke KANAOKA ,  Jung Kyu HAN ,  Gang DUAN ,  Ziyin LIN

IPC: H01L23/00 ,  B32B37/12

CPC classification number: H01L24/75 ,  B32B37/12 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/7531 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83874 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/069 ,  H01L2924/0715

Abstract: The present disclosure relates to a system. The system may include a stage configured to support a substrate. The system may also include a bondhead configured to press a device against the substrate. The system may further include a light source configured to emit UV light towards the stage.

公开(公告)号：US20230086920A1

公开(公告)日：2023-03-23

申请号：US17481245

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Liang HE ,  Jisu JIANG ,  Jung Kyu HAN ,  Gang DUAN ,  Yosuke KANAOKA ,  Jason M. GAMBA ,  Bai NIE ,  Robert Alan MAY ,  Kimberly A. DEVINE ,  Mitchell ARMSTRONG ,  Yue DENG

IPC: H01L23/31 ,  H01L23/22

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for a dam structure on a substrate that is proximate to a die coupled with the substrate, where the dam decreases the risk of die shift during encapsulation material flow over the die during the manufacturing process. The dam structure may fully encircle the die. During encapsulation material flow, the dam structure creates a cavity that moderates the different flow rates of material that otherwise would exert different pressures the sides of the die and cause to die to shift its position on the substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20240178151A1

公开(公告)日：2024-05-30

申请号：US18071901

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Alexander AGUINAGA ,  Gang DUAN ,  Jung Kyu HAN ,  Yosuke KANAOKA ,  Yi LI ,  Robin MCREE ,  Hong Seung YEON

IPC: H01L23/544 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/544 ,  H01L23/15 ,  H01L23/49816

Abstract: Embodiments disclosed herein include a package architecture. In an embodiment, the package architecture comprises a first substrate with a first fiducial mark on a surface of the first substrate. In an embodiment, the package architecture further comprises a second substrate over the first substrate, where the second substrate comprises glass and a second fiducial mark on the second substrate, and where a footprint of the second fiducial mark at least partially overlaps a footprint of the first fiducial mark.

公开(公告)号：US20200312771A1

公开(公告)日：2020-10-01

申请号：US16366661

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20160343680A1

公开(公告)日：2016-11-24

申请号：US15225757

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： Rajasekaran SWAMINATHAN ,  Leonel R. ARANA ,  Yoshihiro TOMITA ,  Yosuke KANAOKA

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11849 ,  H01L2224/16012 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2203/043 ,  H05K2203/083 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

公开(公告)号：US20240088052A1

公开(公告)日：2024-03-14

申请号：US18513015

申请日：2023-11-17

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/381

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20240078702A1

公开(公告)日：2024-03-07

申请号：US17902907

申请日：2022-09-05

Applicant: Intel Corporation

Inventor： Yi LI ,  Hong Seung YEON ,  Nicholas HAEHN ,  Wei LI ,  Raquel DE SOUZA BORGES FERREIRA ,  Minglu LIU ,  Robin McREE ,  Yosuke KANAOKA ,  Gang DUAN ,  Arnab ROY

IPC: G06T7/73 ,  H01L21/68 ,  H01L23/544

CPC classification number: G06T7/74 ,  H01L21/681 ,  H01L23/544 ,  G06T2207/20081 ,  G06T2207/30204 ,  H01L2223/54426

Abstract: A method for recognizing a reference point associated with a fiducial marker including the steps of: obtaining or receiving image data of the fiducial marker; determining the degree of which the image data of the fiducial marker is aligned with one or more reference images; of which if the degree of alignment is determined to be less than an acceptable threshold predicting a set of coordinates of the reference point associated with the fiducial marker; incorporating the set of coordinates with the image data to form a modified image data; and determining the degree of which the modified image data of the fiducial marker is aligned with one or more reference images.

公开(公告)号：US20210043580A1

公开(公告)日：2021-02-11

申请号：US17078897

申请日：2020-10-23

Applicant: Intel Corporation

Inventor： Jesse C. JONES ,  Gang DUAN ,  Jason GAMBA ,  Yosuke KANAOKA ,  Rahul N. MANEPALLI ,  Vishal SHAJAN

IPC: H01L23/544 ,  H01L23/538 ,  H01L21/762

Abstract: An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.