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公开(公告)号：US10076024B2
公开(公告)日：2018-09-11
申请号：US15195090
申请日：2016-06-28
Applicant: Intel Corporation
Inventor： Ruihua Ding , Min Wang , Mo Liu
CPC classification number: H05K1/0245 , H01P1/203 , H01P3/026 , H01P3/04 , H01P3/08 , H01P11/003 , H04B3/32 , H05K1/0216 , H05K1/0228 , H05K3/10 , H05K2201/09236 , H05K2201/09781 , Y10T29/49155
Abstract: This disclosure relates generally to an electronic assembly and method having a first electrical connection point and a second electrical connection point and a differential interconnect coupling the first electrical connection point to the second electrical connection point, the differential interconnect including first and second transmission traces including a interior edges and a exterior edges opposite the interior edges, the second interior edge facing the first interior edge, and stub traces, each stub trace coupled to one of the first and second transmission traces and projecting from one of the first interior edge, the first exterior edge, the second interior edge, and the second exterior edge. A substantially equal number of stub traces project from the first exterior edge and the second exterior edge. At least twice as many stub traces project from the first and second exterior edges as project from the first and second interior edges.
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2.发明申请FIRST AND SECOND DIFFERENTIAL INTERCONNECTS HAVING INTERLEAVED STUB TRACES 审中-公开第一个和第二个具有交互式跟踪的差异互连公开(公告)号：US20170033425A1
公开(公告)日：2017-02-02
申请号：US15195090
申请日：2016-06-28
Applicant: Intel Corporation
Inventor： Ruihua Ding , Min Wang , Mo Liu
CPC classification number: H05K1/0245 , H01P1/203 , H01P3/026 , H01P3/04 , H01P3/08 , H01P11/003 , H04B3/32 , H05K1/0216 , H05K1/0228 , H05K3/10 , H05K2201/09236 , H05K2201/09781 , Y10T29/49155
Abstract: This disclosure relates generally to an electronic assembly and method having a first electrical connection point and a second electrical connection point and a differential interconnect coupling the first electrical connection point to the second electrical connection point, the differential interconnect including first and second transmission traces including a interior edges and a exterior edges opposite the interior edges, the second interior edge facing the first interior edge, and stub traces, each stub trace coupled to one of the first and second transmission traces and projecting from one of the first interior edge, the first exterior edge, the second interior edge, and the second exterior edge. A substantially equal number of stub traces project from the first exterior edge and the second exterior edge. At least twice as many stub traces project from the first and second exterior edges as project from the first and second interior edges.
Abstract translation: 本公开总体上涉及一种具有第一电连接点和第二电连接点的电子组件和方法，以及将第一电连接点耦合到第二电连接点的差分互连，差动互连包括第一和第二传输迹线，包括 内部边缘和与内部边缘相对的外部边缘，面向第一内部边缘的第二内部边缘和短截线迹线，每个短截线迹线耦合到第一和第二传输轨迹中的一个并从第一内部边缘中的一个突出，第一内部边缘 外部边缘，第二内部边缘和第二外部边缘。 从第一外边缘和第二外边缘突出的基本相等数量的短截线迹。 从第一和第二内部边缘起，从第一和第二外部边缘突出的短截线迹线的至少两倍。
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公开(公告)号：US20220021139A1
公开(公告)日：2022-01-20
申请号：US17483913
申请日：2021-09-24
Applicant: Intel Corporation
Inventor： Xiang Li , Shaohua Li , Kai Xiao , Mo Liu , Jingbo Li
Abstract: In one embodiment, a card edge connector includes a housing including a slot to receive a first circuit board. A first plurality of pins extend from within the slot through a bottom of the housing. Each of the first plurality of pins includes a first end to mate with a corresponding contact of the first circuit board and a second end to mate with a corresponding one of a first plurality of contacts of a second circuit board, the second end including a heel portion and a toe portion extending from the heel portion in a direction away from a centerline of the slot. A second plurality of pins extend from within the slot through the bottom of the housing. Each of the second plurality of pins includes a first end to mate with a corresponding contact of the first circuit board and a second end to mate with a corresponding one of a second plurality of contacts of the second circuit board, the second end comprising a heel portion and a toe portion extending from the heel portion in a direction toward the centerline of the slot. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US10965047B2
公开(公告)日：2021-03-30
申请号：US16431498
申请日：2019-06-04
Applicant: Intel Corporation
Inventor： Jong-Ru Guo , Yunhui Chu , Jun Liao , Kai Xiao , Jingbo Li , Yuanhong Zhao , Mo Liu , Beomtaek Lee , James A. McCall , Jaejin Lee , Xiaoning Ye , Zuoguo Wu , Xiang Li
IPC: H05K7/00 , H01R12/71 , H01R13/66 , H01R103/00
Abstract: Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.
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5.发明授权公开(公告)号：US09386690B2
公开(公告)日：2016-07-05
申请号：US14228002
申请日：2014-03-27
Applicant: Intel Corporation
Inventor： Ruihua Ding , Min Wang , Mo Liu
CPC classification number: H05K1/0245 , H01P1/203 , H01P3/026 , H01P3/04 , H01P3/08 , H01P11/003 , H04B3/32 , H05K1/0216 , H05K1/0228 , H05K3/10 , H05K2201/09236 , H05K2201/09781 , Y10T29/49155
Abstract: This disclosure relates generally to an electronic assembly and method having a first electrical connection point and a second electrical connection point and a differential interconnect coupling the first electrical connection point to the second electrical connection point, the differential interconnect including first and second transmission traces including a interior edges and a exterior edges opposite the interior edges, the second interior edge facing the first interior edge, and stub traces, each stub trace coupled to one of the first and second transmission traces and projecting from one of the first interior edge, the first exterior edge, the second interior edge, and the second exterior edge. A substantially equal number of stub traces project from the first exterior edge and the second exterior edge. At least twice as many stub traces project from the first and second exterior edges as project from the first and second interior edges.
Abstract translation: 本公开总体上涉及一种具有第一电连接点和第二电连接点的电子组件和方法，以及将第一电连接点耦合到第二电连接点的差分互连，差动互连包括第一和第二传输迹线，包括 内部边缘和与内部边缘相对的外部边缘，面向第一内部边缘的第二内部边缘和短截线迹线，每个短截线迹线耦合到第一和第二传输轨迹中的一个并从第一内部边缘中的一个突出，第一内部边缘 外部边缘，第二内部边缘和第二外部边缘。 从第一外边缘和第二外边缘突出的基本相等数量的短截线迹。 从第一和第二内部边缘起，从第一和第二外部边缘突出的短截线迹线的至少两倍。
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公开(公告)号：US20190288421A1
公开(公告)日：2019-09-19
申请号：US16431498
申请日：2019-06-04
Applicant: Intel Corporation
Inventor： Jong-Ru Guo , Yunhui Chu , Jun Liao , Kai Xiao , Jingbo Li , Yuanhong Zhao , Mo Liu , Beomtaek Lee , James A. McCall , Jaejin Lee , Xiaoning Ye , Zuoguo Wu , Xiang Li
Abstract: Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.
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公开(公告)号：US20230318211A1
公开(公告)日：2023-10-05
申请号：US18130404
申请日：2023-04-03
Applicant: Intel Corporation
CPC classification number: H01R12/721 , H01R13/5219 , H01R13/5216 , H01R4/023 , H05K7/20236
Abstract: Methods and apparatus relating to liquid-proof edge connector solutions for immersion cooling are described. In one embodiment, a seal prevents a cooling liquid to cause electrical contact with a pin of an edge card to be inserted in a connector. And, an adhesive prevents the cooling liquid to cause electrical contact with a terminal of the connector. Other embodiments are also claimed and disclosed.
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公开(公告)号：US20210203094A1
公开(公告)日：2021-07-01
申请号：US17202961
申请日：2021-03-16
Applicant: Intel Corporation
Inventor： Xiang Li , Mo Liu , Shaohua Li , Jingbo Li , Kai Xiao
Abstract: In one embodiment, a card edge connector includes: a housing having an opening into which a first circuit board is to be inserted; a plurality of pins each having a first end and a second end, the plurality of pins extending from within the opening through a bottom surface of the housing, the first end of the first plurality of pins to mate with a corresponding contact of the first circuit board; and a plurality of ball grid array (BGA) solder balls each adapted at the second end of a corresponding one of the plurality of pins, the plurality of pins to mate with a corresponding conductive area of a second circuit board to which the card edge connector mates via the plurality of BGA solder balls. Other embodiments are described and claimed.
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