公开(公告)号：US09793151B2

公开(公告)日：2017-10-17

申请号：US14568552

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Xavier Brun ,  Arjun Krishnan ,  Mohit Mamodia ,  Dingying Xu

IPC: H01L21/683 ,  H01L21/78 ,  H01L21/304 ,  H01L23/00

CPC classification number: H01L21/6836 ,  H01L21/304 ,  H01L21/78 ,  H01L23/562 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some example forms relate to a stiffener tape for a wafer. The stiffener tape includes a mounting tape and a stiffener removably attached to the mounting tape. The stiffener tape further includes a die attach film attached to the stiffener. Other example forms relate to an electronic assembly that includes a wafer and a stiffener tape attached to the wafer. The stiffener tape includes a die attach film mounted to the wafer. A stiffener is attached to the die attach film and a mounting tape is removably attached to the stiffener. Still other example forms relate to a method that includes forming a stiffener tape which includes a mounting tape, a stiffener removably attached to the mounting tape and a die attach film attached to the stiffener.

公开(公告)号：US09698108B1

公开(公告)日：2017-07-04

申请号：US14998096

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Xavier F. Brun ,  Shweta Agrawal ,  Hao Wu ,  Mohit Mamodia ,  Shengquan E. Ou ,  Hualiang Shi

IPC: H01L21/78 ,  H01L23/58 ,  H01L23/48 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/585 ,  H01L21/76885 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/5283 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Techniques and mechanisms to mitigate contamination of redistribution layer structures disposed on a back side of a semiconductor substrate. In an embodiment, a microelectronics device includes a substrate and integrated circuitry variously formed in or on a front side of the substrate, where vias extend from the integrated circuitry to a back side of the substrate. A redistribution layer disposed on the back side includes a ring structure and a plurality of raised structures each extending from a recess portion that is surrounded by the ring structure. The ring structure and the plurality of raised structures provide contact surfaces for improved adhesion of dicing tape to the back side. In another embodiment, the plurality of raised structures includes dummification comprising dummy structures that are each electrically decoupled from any via extending through the substrate.

公开(公告)号：US10998275B2

公开(公告)日：2021-05-04

申请号：US16465443

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Kyle Yazzie ,  Mohit Mamodia

IPC: H01L23/00 ,  H01L23/06 ,  H01L23/498

Abstract: An apparatus is provided which comprises: a substrate to couple with one or more integrated circuit die(s), an integrated circuit die coupled to the substrate, a metal component coupled to the substrate, wherein the metal component lacks a sealing coating, and a sacrificial metal conductively coupled with the metal component, wherein the sacrificial metal comprises a more anodic metal than the metal component. Other embodiments are also disclosed and claimed.

公开(公告)号：US10598696B2

公开(公告)日：2020-03-24

申请号：US15083082

申请日：2016-03-28

Applicant: INTEL CORPORATION

Inventor： Joseph D. Stanford ,  David Craig ,  Todd P. Albertson ,  Mohit Mamodia ,  Dingying Xu

IPC: G01R1/067 ,  G01R1/073 ,  G01R3/00

Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.

公开(公告)号：US20200006256A1

公开(公告)日：2020-01-02

申请号：US16465443

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Kyle Yazzie ,  Mohit Mamodia

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/06

Abstract: An apparatus is provided which comprises: a substrate to couple with one or more integrated circuit die(s), an integrated circuit die coupled to the substrate, a metal component coupled to the substrate, wherein the metal component lacks a sealing coating, and a sacrificial metal conductively coupled with the metal component, wherein the sacrificial metal comprises a more anodic metal than the metal component. Other embodiments are also disclosed and claimed.

公开(公告)号：US20160172229A1

公开(公告)日：2016-06-16

申请号：US14568552

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Xavier Brun ,  Arjun Krishnan ,  Mohit Mamodia ,  Dingying Xu

IPC: H01L21/683 ,  H01L21/304 ,  H01L21/78

CPC classification number: H01L21/6836 ,  H01L21/304 ,  H01L21/78 ,  H01L23/562 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some example forms relate to a stiffener tape for a wafer. The stiffener tape includes a mounting tape and a stiffener removably attached to the mounting tape. The stiffener tape further includes a die attach film attached to the stiffener. Other example forms relate to an electronic assembly that includes a wafer and a stiffener tape attached to the wafer. The stiffener tape includes a die attach film mounted to the wafer. A stiffener is attached to the die attach film and a mounting tape is removably attached to the stiffener. Still other example forms relate to a method that includes forming a stiffener tape which includes a mounting tape, a stiffener removably attached to the mounting tape and a die attach film attached to the stiffener.

Abstract translation: 一些示例性形式涉及用于晶片的加强带。 加强筋包括可拆卸地附接到安装带的安装带和加强件。 加强筋还包括附着在加强件上的管芯附着膜。 其他示例性形式涉及包括晶片和附接到晶片的加强筋的电子组件。 加强筋包括安装在晶片上的管芯附着膜。 加强件附接到管芯附着膜，并且安装带可拆卸地附接到加强件。 另一个示例形式涉及一种方法，其包括形成加强带，该加强带包括安装带，可移除地附接到安装带的加强件和附接到加强件的管芯附着膜。

公开(公告)号：US10957656B2

公开(公告)日：2021-03-23

申请号：US16641601

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Kyle Yazzie ,  Naga Sivakumar Yagnamurthy ,  Pramod Malatkar ,  Chia-Pin Chiu ,  Mohit Mamodia ,  Mark J. Gallina ,  Rajesh Kumar Neerukatti ,  Joseph Bautista ,  Michael Gregory Drake

IPC: H01L23/40 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498

Abstract: Disclosed herein are integrated circuit (IC) packages with an electronic component having a patterned protective material on a face, as well as related devices and methods. In some embodiments, a computing device may include: an integrated circuit (IC) package with an electronic component having a protective material on the back face of the electronic component, where the protective material is patterned to include an area on the back face of the electronic component that is not covered by the protective material; a circuit board, where the IC package is electrically coupled to the circuit board; and a heat spreader, where the heat spreader is secured to the circuit board and in thermal contact with the area on the back face of the electronic component that is not covered by the protective material.

公开(公告)号：US09406618B2

公开(公告)日：2016-08-02

申请号：US14305439

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： John S. Guzek ,  Ravi K. Nalla ,  Javier Solo Gonzalez ,  Drew Delaney ,  Suresh Pothukuchi ,  Mohit Mamodia ,  Edward Zarbock ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00 ,  H01L25/03 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5384 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/48137 ,  H01L2224/48472 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.

Abstract translation: 一种装置包括具有与无芯基板成一体的贯通硅通孔（TSV）嵌入管芯的无芯基板。 该设备包括连接到TSV管芯并且设置在无芯基板之上的后续管芯。

公开(公告)号：US09165914B2

公开(公告)日：2015-10-20

申请号：US13895546

申请日：2013-05-16

Applicant: Intel Corporation

Inventor： Rahul N. Manepalli ,  Mohit Mamodia ,  David Xu ,  Javier Soto Gonzalez ,  Edward R. Prack

IPC: H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/24 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2924/10253 ,  H01L2924/10523 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a patterned die backside film (DBF) on a backside of a die, wherein the patterned DBF comprises an opening surrounding at least one through silicon via (TSV) pad disposed on the backside of the die.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将图案化的模具背面薄膜（DBF）附接到模具的背面，其中图案化的DBF包括围绕设置在模具背面的至少一个穿过硅通孔（TSV）垫的开口。

公开(公告)号：US11340258B2

公开(公告)日：2022-05-24

申请号：US16817480

申请日：2020-03-12

Applicant: INTEL CORPORATION

Inventor： Joseph D. Stanford ,  David Craig ,  Todd P. Albertson ,  Mohit Mamodia ,  Dingying Xu

IPC: G01R1/067 ,  G01R1/073 ,  G01R3/00

Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.