公开(公告)号：US11527484B2

公开(公告)日：2022-12-13

申请号：US17078897

申请日：2020-10-23

申请人： Intel Corporation

发明人： Jesse C. Jones ,  Gang Duan ,  Jason Gamba ,  Yosuke Kanaoka ,  Rahul N. Manepalli ,  Vishal Shajan

IPC分类号： H01L23/544 ,  H01L21/762 ,  H01L23/538

摘要： An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.

公开(公告)号：US20200027841A1

公开(公告)日：2020-01-23

申请号：US16037504

申请日：2018-07-17

申请人： Intel Corporation

发明人： Jesse C. Jones ,  Gang Duan ,  Jason Gamba ,  Yosuke Kanaoka ,  Rahul N. Manepalli ,  Vishal Shajan

IPC分类号： H01L23/544 ,  H01L21/762 ,  H01L23/538

摘要： An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.

公开(公告)号：US20240355758A1

公开(公告)日：2024-10-24

申请号：US18756926

申请日：2024-06-27

申请人： Intel Corporation

发明人： Steven Adam Klein ,  Jason Gamba ,  Matthew Thomas Guzy ,  Nicholas Steven Haehn ,  Tarek Adly Ibrahim ,  Brandon Christian Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Jacob John Schichtel

IPC分类号： H01L23/544 ,  H01L23/15 ,  H01L23/40

CPC分类号： H01L23/544 ,  H01L23/15 ,  H01L23/4006 ,  H01L2023/4087 ,  H01L2223/54426

摘要： Systems, apparatus, articles of manufacture, and methods to reduce stress between sockets and associated integrated circuit packages having glass cores are disclosed. An example integrated circuit package includes: a semiconductor die, and a substrate including a glass core. The substrate includes a first surface, a second surface opposite the first surface, and a third surface between the first surface and the second surfaces. The first surface supports the semiconductor die. The second surface includes first contacts to electrical couple with second contacts in a socket. At least a portion of the third surface separated and distinct from the glass core.

公开(公告)号：US20240006298A1

公开(公告)日：2024-01-04

申请号：US17855040

申请日：2022-06-30

申请人： Intel Corporation

发明人： Suddhasattwa Nad ,  Steve Cho ,  Marcel Arlan Wall ,  Onur Ozkan ,  Ali Lehaf ,  Yi Yang ,  Jason Scott Steill ,  Gang Duan ,  Brandon C. Marin ,  Jeremy D. Ecton ,  Srinivas Venkata Ramanuja Pietambaram ,  Haifa Hariri ,  Bai Nie ,  Hiroki Tanaka ,  Kyle Mcelhinny ,  Jason Gamba ,  Venkata Rajesh Saranam ,  Kristof Darmawikarta ,  Haobo Chen

IPC分类号： H01L23/498 ,  H01L21/48

CPC分类号： H01L23/49894 ,  H01L23/49816 ,  H01L21/4853 ,  H01L21/481 ,  H01L23/49838

摘要： An electronic device may include an integrated circuit, for instance a semiconductor die. The electronic device may include a substrate having a first layer and a second layer. The first and second layers may include interconnects recessed below a surface of the substrate. The substrate may include a passivation layer directly coupled with portions of the interconnects. A solder resist material may at least partially cover portions of the passivation layer directly coupled with the first interconnect surface.

公开(公告)号：US20240290723A1

公开(公告)日：2024-08-29

申请号：US18114120

申请日：2023-02-24

申请人： Intel Corporation

发明人： Jason Gamba ,  Suddhasattwa Nad ,  Sanjay Tharmarajah ,  Rajeev Ranjan ,  Greg Aponte

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/5384 ,  H01L21/76834 ,  H01L21/76846 ,  H01L23/5329

摘要： An apparatus comprises a first layer comprising a first dielectric material, and first and second regions on a first side of the first layer. The first regions comprise a first surface in a first plane, and each of the second regions comprise a second surface in a second plane spaced away from the first plane by a first distance. Sidewalls extend between the first surface and the second surfaces. The apparatus further comprises a plurality of conductive features, each conductive feature comprising a bottom surface on one of the second surfaces, and a barrier film comprising a second dielectric material that contacts the sidewalls.