公开(公告)号：US20240030204A1

公开(公告)日：2024-01-25

申请号：US17871413

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Gang Duan ,  Hamid R. Azimi ,  Rahul Manepalli ,  Srinivas V. Pietambaram

IPC: H01L25/16 ,  H01L23/427 ,  H01L23/538 ,  G02B6/12

CPC classification number: H01L25/167 ,  H01L23/427 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  G02B6/12004

Abstract: Panel-level high performance computing (HPC) computing architectures and methods for making the same are disclosed. Panel architectures with and without glass cores comprise dielectric layers with interconnect structures (vias, conductive traces) to translate die-level pinouts arranged at a fine pitch to panel-level pinouts arranged at a coarser pitch. Local interconnects and local interconnect components provide for electrical communication between integrated circuit dies in a panel. Coreless panel architectures can comprise a glass reinforcement layer to provide additional mechanical stiffness. The glass reinforcement layer can have interconnect structures and a local interconnect component. Panel embodiments with a glass core or glass reinforcement layer can comprise waveguides and channel a liquid coolant therethrough, and can further comprise photonic integrated circuits. Panel-level manufacturing techniques can enable panels having dimensions larger (e.g., greater than 300 mm) than components fabricated using wafer-level manufacturing techniques.

公开(公告)号：US20230317592A1

公开(公告)日：2023-10-05

申请号：US17711749

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Hamid R. Azimi ,  Sri Chaitra Jyotsna Chavali ,  Tarek A. Ibrahim ,  Wei-Lun K Jen ,  Rahul Manepalli ,  Kevin T. McCarthy

IPC: H01L23/498

CPC classification number: H01L23/49894 ,  H01L23/49822 ,  H01L23/49827

Abstract: In one embodiment, a package substrate includes a substrate core, buildup layers, and one or more conductive traces. The substrate core includes at least one dielectric layer with hollow glass fibers. The buildup layers include dielectric layers below and above the substrate core.

公开(公告)号：US11694898B2

公开(公告)日：2023-07-04

申请号：US16363688

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Jeremy Ecton ,  Bai Nie ,  Rahul Manepalli ,  Marcel Wall

IPC: G09G3/20 ,  H01L21/28 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L21/2815 ,  H01L21/4853 ,  H01L24/17 ,  H01L2224/17051

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, the first die having a first bump pitch, a second die over the package substrate, the second die having a second bump pitch that is greater than the first bump pitch, and a plurality of conductive traces over the package substrate, the plurality of conductive traces electrically coupling the first die to the second die. In an embodiment, a first end region of the plurality of conductive traces proximate to the first die has a first line space (L/S) dimension, and a second end region of the plurality of conductive traces proximate to the second die has a second L/S dimension. In an embodiment, the second L/S dimension is greater than the first L/S dimension.

公开(公告)号：US11501967B2

公开(公告)日：2022-11-15

申请号：US16269357

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Roy Dittler ,  Darko Grujicic ,  Marcel Wall ,  Rahul Manepalli

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.

公开(公告)号：US11177234B2

公开(公告)日：2021-11-16

申请号：US16017393

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Rahul Manepalli ,  Marcel Wall

IPC: H01L23/29 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/532

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a self-assembled monolayers (SAM) layer. The package substrate includes a SAM layer on portions of a conductive pad, where the SAM layer includes light-reflective moieties. The package substrate also includes a via on a surface portion of the conductive pad, and a dielectric on and around the via, the SAM layer, and the conductive pad, where the SAM layer surrounds and contacts a surface of the via. The SAM layer may be an interfacial organic layer. The light-reflective moieties may include a hemicyanine, a cyclic-hemicyanine, an oligothiophene, and/or a conjugated aromatic compound. The SAM layer may include a molecular structure having a first end group of a first monolayer, an intermediate group, a fifth end group of a second monolayer, and one or more of a first and second light-reflective moieties.

公开(公告)号：US20250006646A1

公开(公告)日：2025-01-02

申请号：US18216525

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Xing Sun ,  Srinivas Pietambaram ,  Darko Grujicic ,  Rengarajan Shanmugam ,  Brian Balch ,  Micah Armstrong ,  Qiang Li ,  Marcel Wall ,  Rahul Manepalli

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L25/065

Abstract: Integrated circuit (IC) die packages including a glass with conductive through-glass vias (TGVs). The TGVs are lined with a buffer comprising an inorganic material having a low elastic (Young's) modulus. The buffer may thereby accommodate internal stress between the glass and through via metallization formed over the buffer. The compliant inorganic material may be a metal or metal alloy, for example, different than that of the via metallization. The inorganic material may also be a metal nitride, metal silicide, or metal carbide. A TGV buffer may be one material layer of a stack comprising two or more material layers deposited upon TGV sidewall surfaces. A routing structure may be built-up on at least one side of the glass and IC die assembled to the routing structure. The buffer Ipresent within the TGVs may be absent from metal features of the routing structure.

公开(公告)号：US20240194608A1

公开(公告)日：2024-06-13

申请号：US18080612

申请日：2022-12-13

Applicant: Intel Corporation

Inventor： Gang Duan ,  Rahul Manepalli ,  Srinivas Pietambaram ,  Brandon Marin ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5384 ,  H01L2221/68359

Abstract: An integrated circuit (IC) package comprises a first IC die having first metallization features, a second IC die having second metallization features, and a third IC die having third metallization features. A glass layer is between the third IC die and both of the first IC die and the second IC die. A plurality of first through vias extend through the glass layer, coupling the third metallization features with first ones of the first metallization features and with first ones of the second metallization features. A plurality of second through vias extend through the glass layer. A dielectric material is around the third die and a package metallization is within the dielectric material. The package metallization is coupled to at least one of the first, second, or third IC die, and terminating at a plurality of package interconnect interfaces.

公开(公告)号：US11990427B2

公开(公告)日：2024-05-21

申请号：US17716947

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Gang Duan ,  Deepak Kulkarni ,  Rahul Manepalli ,  Xiaoying Guo

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

公开(公告)号：US11923312B2

公开(公告)日：2024-03-05

申请号：US16366661

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Bai Nie ,  Gang Duan ,  Srinivas Pietambaram ,  Jesse Jones ,  Yosuke Kanaoka ,  Hongxia Feng ,  Dingying Xu ,  Rahul Manepalli ,  Sameer Paital ,  Kristof Darmawikarta ,  Yonggang Li ,  Meizi Jiao ,  Chong Zhang ,  Matthew Tingey ,  Jung Kyu Han ,  Haobo Chen

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/381

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US11769735B2

公开(公告)日：2023-09-26

申请号：US16274086

申请日：2019-02-12

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Gang Duan ,  Deepak Kulkarni ,  Rahul Manepalli ,  Xiaoying Guo

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.