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公开(公告)号：US10892762B2
公开(公告)日：2021-01-12
申请号：US16708972
申请日：2019-12-10
Applicant: Intel Corporation
Inventor： Stefan Tertinek
Abstract: Systems, circuitries, and methods are described for phase-continuous shifting of a reference clock frequency from fREF to NREF for a DPLL that includes a DCO and a feedback loop that generates a feedback signal. The DPLL generates a local oscillator signal based on an analog reference signal having a reference clock frequency fREF and a digital reference signal having the reference clock frequency fREF. In one example, the method includes receiving a target time and at expiration of a first nonzero interval after the target time, generating a subsequent feedback signal having the target reference clock frequency NfREF; at expiration of a second nonzero interval after the target time, generating a subsequent analog reference signal having the target reference clock frequency NfREF; and at expiration of a third nonzero interval after the target time, generating a subsequent digital reference clock signal having the target reference clock frequency NfREF.
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公开(公告)号：US09397689B2
公开(公告)日：2016-07-19
申请号：US14551266
申请日：2014-11-24
Applicant: Intel Corporation
Inventor： Stefan Tertinek , Thomas Mayer , Peter Preyler
CPC classification number: H03M1/82 , H03K5/06 , H03K5/13 , H03K19/00361 , H03L7/0812 , H03M1/002 , H03M1/661 , H03M1/70
Abstract: A digital to time converter is disclosed and includes a code logic and an interpolator. The code logic is configured to receive a first phase signal and a second phase signal and generate a select signal according to the first phase signal and the second phase signal. The interpolator has a bank of inverters. The interpolator is configured to generate an interpolator signal based on the select signal and an input signal.
Abstract translation: 公开了数字到时间转换器，并且包括代码逻辑和内插器。 代码逻辑被配置为接收第一相位信号和第二相位信号，并根据第一相位信号和第二相位信号产生选择信号。 内插器有一组逆变器。 内插器被配置为基于选择信号和输入信号产生内插器信号。
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Patent Agency Ranking
3.发明申请PREDICTIVE TIME-TO-DIGITAL CONVERTER AND METHOD FOR PROVIDING A DIGITAL REPRESENTATION OF A TIME INTERVAL 有权预测的时间 - 数字转换器和提供数字时间间隔的方法公开(公告)号：US20160173118A1
公开(公告)日：2016-06-16
申请号：US14568588
申请日：2014-12-12
Applicant: Intel Corporation
Inventor： Thomas Mayer , Stefan Tertinek
CPC classification number: H03M1/12 , G04F10/005 , H04L5/0048 , H04L7/0037 , H04L7/0045
Abstract: Predictive time-to-digital converters (TDCs) and methods for providing a digital representation of a time interval are disclosed herein. In an example, a TDC can include a delay line, a selection circuit, and a latch circuit. The delay line can include a plurality of delay elements configured to propagate a first edge of a first signal sequentially through the plurality of delay elements. The selection circuit can be configured to receive the first signal, to receive prediction information, and to route the first signal to an input of one of the plurality of delay elements based on the prediction information. The latch circuit can receive a second signal and can latch a plurality of outputs of the delay line upon reception of a second edge of the second signal. An output of the latch circuit can provide an indication of a delay between the first edge and the second edge.
Abstract translation: 这里公开了用于提供时间间隔的数字表示的预测时间 - 数字转换器（TDC）和方法。 在一个示例中，TDC可以包括延迟线，选择电路和锁存电路。 延迟线可以包括多个延迟元件，其被配置成顺序地通过多个延迟元件传播第一信号的第一边缘。 选择电路可以被配置为基于预测信息来接收第一信号，接收预测信息，以及将第一信号路由到多个延迟元件之一的输入。 锁存电路可以接收第二信号，并且可以在接收到第二信号的第二边缘时锁存延迟线的多个输出。 锁存电路的输出可以提供在第一边缘和第二边缘之间的延迟的指示。
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公开(公告)号：US10511311B1
公开(公告)日：2019-12-17
申请号：US16118708
申请日：2018-08-31
Applicant: Intel Corporation
Inventor： Stefan Tertinek
Abstract: Systems, circuitries, and methods are described for phase-continuous shifting of a reference clock frequency from fREF to NREF for a DPLL that includes a DCO and a feedback loop that generates a feedback signal. The DPLL generates a local oscillator signal based on an analog reference signal having a reference clock frequency fREF and a digital reference signal having the reference clock frequency fREF. In one example, the method includes receiving a target time and at expiration of a first nonzero interval after the target time, generating a subsequent feedback signal having the target reference clock frequency NfREF; at expiration of a second nonzero interval after the target time, generating a subsequent analog reference signal having the target reference clock frequency NfREF; and at expiration of a third nonzero interval after the target time, generating a subsequent digital reference clock signal having the target reference clock frequency NfREF.
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公开(公告)号：US09887784B1
公开(公告)日：2018-02-06
申请号：US15278830
申请日：2016-09-28
Applicant: INTEL CORPORATION
Inventor： Stefan Tertinek
IPC: H04B1/40 , H04W88/02 , H04B17/10 , H04B17/345
CPC classification number: H04B17/101 , H04B1/40 , H04B15/04 , H04B17/345 , H04W88/02
Abstract: A user equipment (UE) to compensating for the frequency disturbance. The apparatus may include baseband circuitry and radio frequency (RF) circuitry. The baseband circuitry may detect a request for connectivity circuitry to perform an operation that generates a signal creating a frequency disturbance at the RF circuitry and send operation information indicating a type of the operation to radio frequency (RF) circuitry. The RF circuitry may include a processor and a phase lock loop (PLL) subsystem. The processor may receive the operation information; determine timing information correlating to the operation information; and send the timing information to a phase lock loop (PLL) subsystem indicating the type of the operation and a time of the operation. The PLL subsystem may generate an inverse signal to compensate for the frequency disturbance.
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6.发明授权Predictive time-to-digital converter and method for providing a digital representation of a time interval 有权用于提供时间间隔的数字表示的预测性时间 - 数字转换器和方法公开(公告)号：US09479187B2
公开(公告)日：2016-10-25
申请号：US14568588
申请日：2014-12-12
Applicant: Intel Corporation
Inventor： Thomas Mayer , Stefan Tertinek
CPC classification number: H03M1/12 , G04F10/005 , H04L5/0048 , H04L7/0037 , H04L7/0045
Abstract: Predictive time-to-digital converters (TDCs) and methods for providing a digital representation of a time interval are disclosed herein. In an example, a TDC can include a delay line, a selection circuit, and a latch circuit. The delay line can include a plurality of delay elements configured to propagate a first edge of a first signal sequentially through the plurality of delay elements. The selection circuit can be configured to receive the first signal, to receive prediction information, and to route the first signal to an input of one of the plurality of delay elements based on the prediction information. The latch circuit can receive a second signal and can latch a plurality of outputs of the delay line upon reception of a second edge of the second signal. An output of the latch circuit can provide an indication of a delay between the first edge and the second edge.
Abstract translation: 这里公开了用于提供时间间隔的数字表示的预测时间 - 数字转换器（TDC）和方法。 在一个示例中，TDC可以包括延迟线，选择电路和锁存电路。 延迟线可以包括多个延迟元件，其被配置成顺序地通过多个延迟元件传播第一信号的第一边缘。 选择电路可以被配置为基于预测信息来接收第一信号，接收预测信息，以及将第一信号路由到多个延迟元件之一的输入。 锁存电路可以接收第二信号，并且可以在接收到第二信号的第二边缘时锁存延迟线的多个输出。 锁存电路的输出可以提供在第一边缘和第二边缘之间的延迟的指示。
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公开(公告)号：US20160149584A1
公开(公告)日：2016-05-26
申请号：US14551266
申请日：2014-11-24
Applicant: Intel Corporation
Inventor： Stefan Tertinek , Thomas Mayer , Peter Preyler
CPC classification number: H03M1/82 , H03K5/06 , H03K5/13 , H03K19/00361 , H03L7/0812 , H03M1/002 , H03M1/661 , H03M1/70
Abstract: A digital to time converter is disclosed and includes a code logic and an interpolator. The code logic is configured to receive a first phase signal and a second phase signal and generate a select signal according to the first phase signal and the second phase signal. The interpolator has a bank of inverters. The interpolator is configured to generate an interpolator signal based on the select signal and an input signal.
Abstract translation: 公开了数字到时间转换器，并且包括代码逻辑和内插器。 代码逻辑被配置为接收第一相位信号和第二相位信号，并根据第一相位信号和第二相位信号产生选择信号。 内插器有一组逆变器。 内插器被配置为基于选择信号和输入信号产生内插器信号。
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