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公开(公告)号:US20190098085A1
公开(公告)日:2019-03-28
申请号:US15718756
申请日:2017-09-28
Applicant: Intel Corporation
Inventor: Yi ZOU , Arun RAGHUNATH , Anjaneya Reddy CHAGAM REDDY
IPC: H04L29/08 , H04L12/931
Abstract: A method performed by a networking switch in an object storage system. The method includes receiving a first packet from a network comprising an object ID and a data object. The method includes generating a replica for the data object. The method includes generating an object ID for the replica of the data object. The method includes determining a destination storage node for the replica of the data object. The method includes sending a second packet from the networking switch to the destination storage node. The second packet includes the object ID for the replica of the data object and the replica of the data object.
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公开(公告)号:US20210326270A1
公开(公告)日:2021-10-21
申请号:US17359554
申请日:2021-06-26
Applicant: Intel Corporation
Inventor: Yi ZOU , Arun RAGHUNATH , Scott D. PETERSON , Sujoy SEN , Yadong LI
IPC: G06F12/1072 , G06F3/06
Abstract: Examples described herein relate to a network interface device comprising circuitry to receive an access request with a target logical block address (LBA) and based on a target media of the access request storing at least one object, translate the target LBA to an address and access content in the target media based on the address. In some examples, translate the target LBA to an address includes access a translation entry that maps the LBA to one or more of: a physical address or a virtual address. In some examples, translate the target LBA to an address comprises: request a software defined storage (SDS) stack to provide a translation of the LBA to one or more of: a physical address or a virtual address and store the translation into a mapping table for access by the circuitry. In some examples, at least one entry that maps the LBA to one or more of: a physical address or a virtual address is received before receipt of an access request.
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公开(公告)号:US20180090201A1
公开(公告)日:2018-03-29
申请号:US15276588
申请日:2016-09-26
Applicant: INTEL CORPORATION
Inventor: Wei WU , Jawad B. KHAN , Sanjeev N. TRIKA , Yi ZOU
CPC classification number: G11C11/5628 , G06F11/1044 , G06F11/1072 , G11C11/5642 , G11C16/0483 , G11C16/3427 , G11C16/349 , G11C29/021 , G11C29/028 , G11C2029/0409
Abstract: Provided are a method and apparatus for programming non-volatile memory using a multi-cell storage cell group to provide error location information for retention errors. Each storage cell in the non-volatile memory is programmed with threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller organizes the storage cells into storage cell groups, each storing m bits of information programmed with the threshold voltage levels. A determination is made of one threshold voltage level to use for each of the storage cells in the storage cell group to program a selected k bits in the storage cell group with threshold voltage levels defining one of a plurality of valid states. The threshold voltage levels for at least one of the storage cells of the storage cell group in any two valid states differ by at least two threshold voltage levels.
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公开(公告)号:US20200319915A1
公开(公告)日:2020-10-08
申请号:US16907927
申请日:2020-06-22
Applicant: Intel Corporation
Inventor: Arun RAGHUNATH , Yi ZOU , Tushar Sudhakar GOHAD , Anjaneya R. CHAGAM REDDY , Sujoy SEN
Abstract: A method is described. The method includes performing the following with a storage end transaction agent within a storage sled of a rack mounted computing system: receiving a request to perform storage operations with one or more storage devices of the storage sled, the request specifying an all-or-nothing semantic for the storage operations; recognizing that all of the storage operations have successfully completed; after all of the storage operations have successfully completed, reporting to a CPU side transaction agent that sent the request that all of the storage operations have successfully completed.
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公开(公告)号:US20190044853A1
公开(公告)日:2019-02-07
申请号:US15870709
申请日:2018-01-12
Applicant: INTEL CORPORATION
Inventor: Arun RAGHUNATH , Anjaneya Reddy CHAGAM REDDY , Yi ZOU
IPC: H04L12/773 , G06F3/06 , H04L29/08 , G06F17/30
Abstract: In one embodiment, switch-assisted data storage network traffic management in a data storage center consolidates data placement requests and data placement acknowledgements to reduce network traffic. Other aspects are described herein.
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公开(公告)号:US20190108095A1
公开(公告)日:2019-04-11
申请号:US16213563
申请日:2018-12-07
Applicant: Intel Corporation
Inventor: Yi ZOU , Arun RAGHUNATH , Anjaneya R. CHAGAM REDDY , Sujoy SEN , Tushar Sudhakar GOHAD
Abstract: To reduce the cost of ensuring the integrity of data stored in distributed data storage systems, a storage-side system provides data integrity services without the involvement of the host-side data storage system. Processes for storage-side data integrity include maintaining a block ownership map and performing data integrity checking and repair functions in storage target subsystems. The storage target subsystems are configured to efficiently manage data stored remotely using a storage fabric protocol such as NVMe-oF. The storage target subsystems can be implemented in a disaggregated storage computing system on behalf of a host-side distributed data storage system, such as software-defined storage (SDS) system.
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公开(公告)号:US20180040367A1
公开(公告)日:2018-02-08
申请号:US15228699
申请日:2016-08-04
Applicant: INTEL CORPORATION
Inventor: Wei WU , Yi ZOU , Jawad B. KHAN , Xin GUO
CPC classification number: G11C11/5628 , G06F3/0608 , G06F3/0661 , G06F3/0688 , G11C7/1006 , G11C11/5642 , G11C16/10 , G11C2211/5641 , G11C2211/5648
Abstract: Provided are a method and apparatus for endurance friendly programming using lower voltage thresholds. A non-volatile memory has storage cells organized as pages programmed using a first number of threshold voltage levels. The storage cells are organized into storage cell groups to which data is written. Each storage cell group is programmed to store a first number of bits of information. A memory controller selects a second number of bits of information from pages less than the first number of bits of information. The memory controller programs the storage cells of the storage cell group using threshold voltage levels from a second number of threshold voltage levels, wherein the second number of threshold voltage levels is less than the first number of threshold voltage levels and comprises a lowest of the first number of threshold voltage levels.
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8.
公开(公告)号:US20180039429A1
公开(公告)日:2018-02-08
申请号:US15228729
申请日:2016-08-04
Applicant: INTEL CORPORATION
Inventor: Wei WU , Yi ZOU , Jawad B. KHAN , Xin GUO
IPC: G06F3/06 , G06F12/1009 , G11C11/56
CPC classification number: G06F3/0616 , G06F3/0644 , G06F3/0688 , G06F12/1009 , G06F2212/1036 , G06F2212/2022 , G06F2212/7201 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C2211/5641 , G11C2211/5648
Abstract: Provided are an apparatus, method, and system for programming a multi-cell storage cell group. A non-volatile memory has storage cells. Each storage cell is programmed with information using a plurality of threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller is configured to program the storage cells and to organize the storage cells in the non-volatile memory into storage cell groups. Each storage cell group stores a number of bits of information and each of the storage cells in each of the storage cell groups is programmed with the plurality of threshold voltage levels. The memory controller selects bits from the pages to write for one storage cell group and determines at least one threshold voltage level to use for each of the storage cells in the storage cell group to program the selected bits in the storage cell group.
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