公开(公告)号：US20250096114A1

公开(公告)日：2025-03-20

申请号：US18469810

申请日：2023-09-19

Applicant: Intel Corporation

Inventor： Robin Chao ,  Chiao-Ti Huang ,  Guowei Xu ,  Ting-Hsiang Hung ,  Tao Chu ,  Feng Zhang ,  Chia-Ching Lin ,  Yang Zhang ,  Anand Murthy ,  Conor P. Puls

IPC: H01L23/522 ,  H01L23/528

Abstract: Techniques to form semiconductor devices can include one or more via structures having substrate taps. A semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region). The gate structure may extend over the semiconductor regions of any number of devices along a given direction. The gate structure may be interrupted, for example, between two transistors with a via structure that extends through an entire thickness of the gate structure and includes a conductive core. The via structure has a conductive foot portion beneath the gate structure and a conductive arm portion extending from the conductive foot portion along a height of the gate structure. The conductive foot portion has a greater width along the given direction than any part of the conductive arm portion. The via structure may further include one or more dielectric layers between the conductive arm portion and the gate structure.

公开(公告)号：US20250006734A1

公开(公告)日：2025-01-02

申请号：US18216493

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Yanbin Luo ,  Paul Packan ,  Guowei Xu ,  Chiao-Ti Huang ,  Robin Chao ,  Feng Zhang ,  Ting-Hsiang Hung ,  Chia-Ching Lin ,  Yang Zhang ,  Chung-Hsun Lin

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

Abstract: An integrated circuit (IC) device includes a stripe of material perpendicular to, and spanning between, semiconductor structures with multiple widths, and the stripe is between transistors with channel regions of differing widths in the semiconductor structures. The material stripes cover transition portions between different widths of the semiconductor structures. The semiconductor structures may be channel structures of different types, including groups of fins or nanoribbons. Channel regions of differing widths may include more or fewer fins or narrower or wider nanoribbons. The channel regions may have alternating conductivity types, n- and p-type.

公开(公告)号：US20240088265A1

公开(公告)日：2024-03-14

申请号：US17940194

申请日：2022-09-08

Applicant: Intel Corporation

Inventor： Tao Chu ,  Guowei Xu ,  Feng Zhang ,  Ting-Hsiang Hung ,  Chia-Ching Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L29/0669 ,  H01L29/78618

Abstract: Techniques are provided herein to form semiconductor devices having epitaxial growth laterally extending between inner spacer structures to mitigate issues caused by the inner spacer structures either being too thick or too thin. A directional etch is performed along the side of a multilayer fin to create a relatively narrow opening for a source or drain region to increase the usable fin space for forming the inner spacer structures. After the inner spacer structures are formed around ends of the semiconductor layers within the fin, the exposed ends of the semiconductor layers are laterally recessed inwards from the outermost sidewalls of the inner spacer structures. Accordingly, the epitaxial source or drain region is grown from the recessed semiconductor ends and thus fills in the recessed regions between the spacer structures.

公开(公告)号：US20250107156A1

公开(公告)日：2025-03-27

申请号：US18471710

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Robin Chao ,  Jaladhi Mehta ,  Tao Chu ,  Guowei Xu ,  Ting-Hsiang Hung ,  Feng Zhang ,  Yang Zhang ,  Chia-Ching Lin ,  Chung-Hsun Lin ,  Anand Murthy

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: Techniques are provided herein to form an integrated circuit having dielectric material formed in cavities beneath source or drain regions. The cavities may be formed within subfin portions of semiconductor devices. In one such example, a FET (field effect transistor) includes a gate structure extending around a fin or any number of nanowires of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction substantially orthogonal to the first direction. A dielectric fill may be formed in a recess beneath the source or drain regions, or a dielectric liner may be formed on sidewalls of the recess, to prevent epitaxial growth of the source or drain regions from the subfins. Removal of the semiconductor subfin from the backside may then be performed without causing damage to the source or drain regions.

公开(公告)号：US20250089310A1

公开(公告)日：2025-03-13

申请号：US18466246

申请日：2023-09-13

Applicant: Intel Corporation

Inventor： Ting-Hsiang Hung ,  Yang Zhang ,  Robin Chao ,  Guowei Xu ,  Tao Chu ,  Chiao-Ti Huang ,  Feng Zhang ,  Chia-Ching Lin ,  Anand Murthy

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

Abstract: Techniques are provided to form semiconductor devices that include through-gate structures (e.g., gate cut structures or conductive via structures) that have an airgap spacer between the structure and the adjacent gate electrode. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region) that extends from a first source or drain region to a second source or drain region. A through-gate structure may extend in a third direction through an entire thickness of the gate structure and adjacent to the semiconductor region along the second direction. The through-gate structure may be a dielectric structure (e.g., a gate cut) or a conductive structure (e.g., a via). In either case, an airgap spacer exists between the through-gate structure and the gate structure.

公开(公告)号：US20250140649A1

公开(公告)日：2025-05-01

申请号：US18498340

申请日：2023-10-31

Applicant: Intel corporation

Inventor： Feng Zhang ,  Tao Chu ,  Minwoo Jang ,  Yanbin Luo ,  Guowei Xu ,  Ting-Hsiang Hung ,  Chiao-Ti Huang ,  Robin Chao ,  Chia-Ching Lin ,  Yang Zhang ,  Kan Zhang

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/778 ,  H01L29/786

Abstract: An IC device may include a semiconductor structure and a backside semiconductor structure over the semiconductor structure. The semiconductor structure and backside semiconductor structure may constitute the source or drain region of a transistor. The backside semiconductor structure may be closer to the backside of a substrate of the IC device than the semiconductor structure. The backside semiconductor structure may be formed at a lower temperature than the semiconductor structure. The backside semiconductor structure may have one or more different materials from the semiconductor structure. For instance, a semiconductor material in the backside semiconductor structure may have a different crystal direction from a semiconductor material in the semiconductor structure. As another example, the backside semiconductor structure may have one or more different chemical compounds from the semiconductor structure. The backside semiconductor structure may be over a backside via that can couple the backside semiconductor structure to a backside metal layer.

公开(公告)号：US20250087530A1

公开(公告)日：2025-03-13

申请号：US18463436

申请日：2023-09-08

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Tao Chu ,  Guowei Xu ,  Robin Chao ,  Feng Zhang ,  Yang Zhang ,  Ting-Hsiang Hung ,  Anand Murthy

IPC: H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L27/088 ,  H01L27/12

Abstract: Techniques are provided to form semiconductor devices where portions of the gate structure (e.g., foot structures) adjacent to the subfins have been removed. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The gate cut includes dielectric lobe structures that extend outwards from the sidewalls of the gate cut. The lobe structures effectively replace foot structures of the gate structure between the gate cut and subfin portions of the semiconductor fins. Removing the gate foot structures contributes to the reduction of the parasitic capacitance in the semiconductor device.

公开(公告)号：US20240222484A1

公开(公告)日：2024-07-04

申请号：US18092152

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Kevin P. O'Brien ,  Ashish Verma Penumatcha ,  Chelsey Dorow ,  Kirby Maxey ,  Carl H. Naylor ,  Tao Chu ,  Guowei Xu ,  Uygar Avci ,  Feng Zhang ,  Ting-Hsiang Hung ,  Ande Kitamura ,  Mahmut Sami Kavrik

IPC: H01L29/76 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7606 ,  H01L21/02568 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/775

Abstract: Transistors and integrated circuitry including a 2D channel material layer within a stack of material layers further including one or more insulator (e.g., dielectric) materials above and/or below the 2D channel material layer. These supporting insulator layers may be non-sacrificial while other material layers within a starting material stack may be sacrificial, replaced, for example, with gate insulator and/or gate material. In some exemplary embodiments, the 2D channel material is a metal chalcogenide and the supporting insulator layer is advantageously a dielectric material composition having a low dielectric constant.

公开(公告)号：US20240088217A1

公开(公告)日：2024-03-14

申请号：US17940195

申请日：2022-09-08

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Chia-Ching Lin ,  Yanbin Luo ,  Ting-Hsiang Hung ,  Feng Zhang ,  Guowei Xu

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L29/7856

Abstract: Techniques are provided herein to form semiconductor devices that include a layer across an upper surface of a dielectric fill between devices and configured to prevent or otherwise reduce recessing of the dielectric fill. In this manner, the layer may be referred to as a barrier layer or recess-inhibiting layer. The semiconductor regions of the devices extend above a subfin region that may be native to the substrate. These subfin regions are separated from one another using a dielectric fill that acts as a shallow trench isolation (STI) structure to electrically isolate devices from one another. A barrier layer is formed over the dielectric fill early in the fabrication process to prevent or otherwise reduce the dielectric fill from recessing during subsequent processing. The layer may include oxygen and a metal, such as aluminum.

公开(公告)号：US20250169130A1

公开(公告)日：2025-05-22

申请号：US18515626

申请日：2023-11-21

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Yanbin Luo ,  Paul Packan ,  Guowei Xu ,  Chiao-Ti Huang ,  Robin Chao ,  Feng Zhang ,  Ting-Hsiang Hung ,  Chia-Ching Lin ,  Yang Zhang ,  Kan Zhang ,  Chung-Hsun Lin ,  Anand S. Murthy

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66

Abstract: Fabrication methods for integrated circuit (IC) structures and devices with different nanoribbon thicknesses are disclosed. In one example, an IC structure includes a stack of nanoribbons stacked above one another over the support, including a first nanoribbon with a first channel region and a second nanoribbon with a second channel region, where the first channel region has a first thickness and the second channel region has a second thickness, and where the first thickness of the first channel region is different (e.g., greater) than the second thickness of the second channel region.