-
公开(公告)号：US10102004B2
公开(公告)日：2018-10-16
申请号：US14226980
申请日：2014-03-27
摘要： Embodiments relate tracking utilization in a multithreading (MT) computer system. According to one aspect, a computer system includes a configuration with a core configured to operate in a MT that supports multiple threads on shared resources of the core. The core is configured to perform a method that includes resetting a plurality of utilization counters. The utilization counters include a plurality of sets of counters. During each clock cycle on the core, a set of counters is selected from the plurality of sets of counters. The selecting is based on a number of currently active threads on the core. In addition, during each clock cycle a counter in the selected set of counters is incremented based on an aggregation of one or more execution events at the multiple threads of the core. Values of the utilization counters are provided to a software program.
-
公开(公告)号：US20170003964A1
公开(公告)日：2017-01-05
申请号：US14854255
申请日：2015-09-15
CPC分类号： G06F9/30043 , G06F3/0608 , G06F3/064 , G06F3/0644 , G06F3/067
摘要： Aspects include a computer-implemented method for receiving an instruction at a processor, the instruction associated with a memory block having an address. A clear indicator that indicates whether the memory block is in a cleared state is assessed by the processor. The cleared state is a state of the memory block in which the memory block does not have any data stored therein. The method also includes determining based on the clear indicator whether the memory block is in the cleared state.
-
公开(公告)号：US20170003893A1
公开(公告)日：2017-01-05
申请号：US14854248
申请日：2015-09-15
IPC分类号： G06F3/06
CPC分类号： G06F3/0617 , G06F3/0604 , G06F3/064 , G06F3/0653 , G06F3/0673
摘要： Aspects include a computer-implemented method that includes receiving an instruction at a processor, the instruction associated with a memory block having an address, and accessing a state indicator by the processor. The state indicator indicates whether the memory block is in a pre-defined state, and the state indicator is accessible by the processor independent of the memory block. The method also includes, based on the state indicator indicating that the memory block is in the pre-defined state, inspecting a subset of data values in the memory block, and identifying the pre-defined state of the memory block based on the subset of data values.
摘要翻译： 方面包括计算机实现的方法，其包括在处理器处接收指令，与具有地址的存储器块相关联的指令，以及由处理器访问状态指示符。 状态指示器指示存储器块是否处于预定义状态，并且处理器可以独立于存储器块访问状态指示符。 该方法还包括：基于指示存储器块处于预定义状态的状态指示符，检查存储器块中的数据值的子集，以及基于存储器块的子集来识别存储块的预定义状态 数据值。
-
公开(公告)号：US20130332709A1
公开(公告)日：2013-12-12
申请号：US13966764
申请日：2013-08-14
发明人： Jane H. Bartik , Lisa C. Heller , Damian L. Osisek , Donald W. Schmidt , Patrick M. West, JR. , Phil C. Yeh
IPC分类号： G06F9/30
CPC分类号： G06F3/0656 , G06F3/061 , G06F3/0619 , G06F3/0653 , G06F3/0673 , G06F9/30145 , G06F12/06 , G06F12/0802 , G06F13/24 , G06F2212/461
摘要： A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.
摘要翻译： 测量采样设备以指定的采样间隔拍摄正在其中执行的中央处理单元（CPU）的快照，以收集与在CPU上执行的任务有关的数据。 收集的数据被存储在缓冲器中，并且在选定的时间提供中断以从缓冲器中移除数据以使其能够重复使用。 在每个采样之后不采取中断，但是在足够的时间去除数据并最小化数据丢失。
-
公开(公告)号：US10394488B2
公开(公告)日：2019-08-27
申请号：US15835618
申请日：2017-12-08
发明人： Jane H. Bartik , Lisa C. Heller , Damian L. Osisek , Donald W. Schmidt , Patrick M. West, Jr. , Phil C. Yeh
IPC分类号： G06F3/06 , G06F13/24 , G06F9/30 , G06F12/06 , G06F12/0802
摘要： A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.
-
公开(公告)号：US20190146916A1
公开(公告)日：2019-05-16
申请号：US15809049
申请日：2017-11-10
发明人： Nicholas C. Matsakis , Craig R. Walters , Jane H. Bartik , Chung-Lung K. Shum , Elpida Tzortzatos
IPC分类号： G06F12/084
摘要： A shared cache line is concurrently modified by multiple processors of a computing environment. The concurrent modification is performed based, at least, on receiving one or more architected instructions (Fetch due to Non-Coherent Store instructions) that permit multiple processors to concurrently update the shared cache line absent obtaining a lock or having exclusive ownership of the data.
-
公开(公告)号：US10095523B2
公开(公告)日：2018-10-09
申请号：US14824123
申请日：2015-08-12
摘要： Embodiments relate tracking utilization in a multithreading (MT) computer system. According to one aspect, a computer system includes a configuration with a core configured to operate in a MT that supports multiple threads on shared resources of the core. The core is configured to perform a method that includes resetting a plurality of utilization counters. The utilization counters include a plurality of sets of counters. During each clock cycle on the core, a set of counters is selected from the plurality of sets of counters. The selecting is based on a number of currently active threads on the core. In addition, during each clock cycle a counter in the selected set of counters is incremented based on an aggregation of one or more execution events at the multiple threads of the core. Values of the utilization counters are provided to a software program.
-
8.发明授权公开(公告)号：US09495156B1
公开(公告)日：2016-11-15
申请号：US15090909
申请日：2016-04-05
发明人： Khary J. Alexander , Jane H. Bartik , Jatin Bhartia , James J. Bonanno , Adam B. Collura , Jang-Soo Lee , James R. Mitchell , Anthony Saporito
CPC分类号： G06F9/3806 , G06F9/30021 , G06F9/30043 , G06F9/30058 , G06F9/30145 , G06F9/3834 , G06F9/3838 , G06F9/3844 , G06F9/3855 , G06F9/3861
摘要： Technical solutions are described for dynamically managing an operand-store-compare (OSC) prediction table for load and store operations executed out-of-order. One general aspect includes a method that includes receiving a request to retire a queue entry corresponding to an instruction. The method also includes identifying an OSC prediction for the instruction based on an OSC prediction table entry, where the OSC prediction indicates if the instruction is predicted to hit an OSC hazard. The method also includes determining if the instruction hit the OSC hazard. The method also includes in response to the OSC prediction indicating that the instruction is predicted to hit the OSC hazard and the instruction not hitting the OSC hazard, invalidating the OSC prediction table entry corresponding to the instruction. The present document further describes examples of other aspects such as methods, computer products.
摘要翻译： 描述了用于动态管理操作数存储比较（OSC）预测表的技术解决方案，用于无序执行的加载和存储操作。 一般的方面包括一种方法，包括接收对与指令相对应的队列条目进行退出的请求。 该方法还包括基于OSC预测表条目来识别针对该指令的OSC预测，其中OSC预测指示该指令是否被预测为触发OSC危险。 该方法还包括确定指令是否触发了OSC危险。 该方法还包括响应于OSC预测，指示该指令被预测为触发OSC危险，并且该指令未触及OSC危险，使与该指令相对应的OSC预测表项无效。 本文件进一步描述了诸如方法，计算机产品的其它方面的示例。
-
公开(公告)号：US20160098273A1
公开(公告)日：2016-04-07
申请号：US14506099
申请日：2014-10-03
IPC分类号： G06F9/30
CPC分类号： G06F3/064 , G06F3/0604 , G06F3/0622 , G06F3/0673 , G06F9/30003 , G06F9/3004 , G06F9/3013 , G06F11/30 , G06F11/3024 , G06F11/3096 , G06F11/348 , G06F2201/88
摘要： A system and method for implementing a servicing instruction for a plurality of counters that includes determining a counter set based on the servicing instruction, whether access is authorized to the counter set, and a block of storage in a memory based on the service instruction. In response to the determining that the access is authorized, the system and method extracts the plurality of counters within the counter set in response to the determining that the access is authorized and storing the plurality of counters in the block of storage.
-
10.发明申请公开(公告)号：US20150347150A1
公开(公告)日：2015-12-03
申请号：US14824123
申请日：2015-08-12
CPC分类号： G06F9/3851 , G06F1/10 , G06F9/30145 , G06F9/3861 , G06F9/5061 , G06F9/5083
摘要： Embodiments relate tracking utilization in a multithreading (MT) computer system. According to one aspect, a computer system includes a configuration with a core configured to operate in a MT that supports multiple threads on shared resources of the core. The core is configured to perform a method that includes resetting a plurality of utilization counters. The utilization counters include a plurality of sets of counters. During each clock cycle on the core, a set of counters is selected from the plurality of sets of counters. The selecting is based on a number of currently active threads on the core. In addition, during each clock cycle a counter in the selected set of counters is incremented based on an aggregation of one or more execution events at the multiple threads of the core. Values of the utilization counters are provided to a software program.
摘要翻译： 实施例涉及多线程（MT）计算机系统中的跟踪利用。 根据一个方面，一种计算机系统包括具有被配置为在支持所述核心的共享资源上的多个线程的MT中操作的核心的配置。 核心被配置为执行包括重置多个利用计数器的方法。 利用计数器包括多组计数器。 在核心的每个时钟周期期间，从多组计数器中选择一组计数器。 该选择基于核心上当前活动的线程数量。 此外，在每个时钟周期期间，所选择的一组计数器中的计数器基于核心的多个线程处的一个或多个执行事件的聚合而递增。 利用率计数器的值被提供给软件程序。
-
-
-
-
-
-
-
-
-
搜索结果
38 条记录 (耗时 0.024 秒)
