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    Sorting non-volatile memories
    1.
    发明授权
    Sorting non-volatile memories 有权
    排序非易失性存储器

    公开(公告)号：US09530522B1

    公开(公告)日：2016-12-27

    申请号：US15066178

    申请日：2016-03-10

    申请人： International Business Machines Corporation

    发明人： Jeffrey W. Christensen ,  Phillip E. Christensen ,  Daniel E. Moore ,  Antoine G. Sater ,  Jung H. Yoon

    IPC分类号： H01L21/20 ,  G11C29/38 ,  G11C29/44

    CPC分类号： G11C29/38 ,  G11C16/04 ,  G11C16/349 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/56008

    摘要： A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.

    摘要翻译： 用于排序非易失性随机存取存储器（NVRAMS）的计算机实现的方法包括在多个测试会话中测试多个NVRAMS中的每一个的故障度量，以捕获对应于多个NVRAMS的故障量度数据。 该方法还包括根据故障度量数据确定作为多个NVRAMS中的每一个的测试周期的功能的故障量度中的趋势，并且基于故障度量中的趋势作为函数将所述多个NVRAMS分组为组 测试周期。 本文还公开了相应的计算机程序产品和计算机系统。

    USING PERSISTANT MEMORY REGIONS WITHIN MEMORY DEVICES TO COLLECT SERIAL PRESENCE DETECT AND PERFORMANCE DATA
    7.
    发明申请
    USING PERSISTANT MEMORY REGIONS WITHIN MEMORY DEVICES TO COLLECT SERIAL PRESENCE DETECT AND PERFORMANCE DATA 有权
    在存储器件中使用记忆体区域以收集串行存在检测和性能数据

    公开(公告)号：US20150006967A1

    公开(公告)日：2015-01-01

    申请号：US14461662

    申请日：2014-08-18

    申请人： International Business Machines Corporation

    发明人： Tu To Dang ,  John Q. Hernandez ,  Sumeet Kochar ,  Jung H. Yoon

    IPC分类号： G06F11/22 ,  G06F1/32 ,  G06F12/02

    CPC分类号： G06F11/2284 ,  G06F1/3225 ,  G06F11/3037 ,  G06F11/3058 ,  G06F11/3409 ,  G06F11/3419 ,  G06F11/3476 ,  G06F12/0246 ,  G06F2201/88 ,  G11C7/20 ,  G11C11/1673 ,  G11C11/4072 ,  G11C2029/0407 ,  G11C2029/4402 ,  Y02D10/34

    摘要： An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.

    摘要翻译： 提供了一种用于确定新安装到计算机系统中的存储器件的通电小时偏移的方法，其从当前的电源开启时间值中减去存储器件的当前通电时间计数 的电源，其向计算机系统内的存储器装置提供操作电力。 响应于计算机系统断电，通过从计算机系统电源的当前通电时间值中减去存储器的电源开启时间偏移来确定存储器件的累积上电时间。 所确定的上电时间偏移和累积的上电时间值被保存到存储器装置的电可擦除可编程只读存储器的一个或多个指定字节中，该可擦除可编程只读存储器可用于存储器控制器的数据存储 并且其中存储在其中的数据在操作功率丢失到存储器设备，存储器控制器或计算机系统之后持续。

    AUTOMATED DATA-DRIVEN CLOSED-LOOP-FEEDBACK METHOD FOR ADAPTIVE & COMPARATIVE QUALITY CONTROL IN A DISCRETE DATA AGGREGATION ENVIRONMENT
    8.
    发明申请
    AUTOMATED DATA-DRIVEN CLOSED-LOOP-FEEDBACK METHOD FOR ADAPTIVE & COMPARATIVE QUALITY CONTROL IN A DISCRETE DATA AGGREGATION ENVIRONMENT 有权
    自动数据驱动闭环反馈方法，用于分散数据聚合环境中的自适应和比较质量控制

    公开(公告)号：US20140121805A1

    公开(公告)日：2014-05-01

    申请号：US13661400

    申请日：2012-10-26

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Robert A. DiMarco ,  Vincent J. Giancaspro ,  Michael J. Whitney ,  Feng Xue ,  Jung H. Yoon

    IPC分类号： G06F19/00

    CPC分类号： G06Q10/06 ,  G06Q10/00 ,  G06Q10/06395 ,  G06Q30/00

    摘要： A method for determining quality includes receiving supplier quality data from a supplier. The supplier quality data includes discrete quality data. The supplier quality data is for a quantity of a component supplied to a company or for a service provided on behalf of the company over a supplier measurement period. The method includes aggregating quality data from two or more suppliers. The quality data is for the supplied component or provided service over a baseline time period. The method includes determining a quality benchmark using the aggregated quality data and setting one or more alarm levels. The alarm levels are based on the quality benchmark of the aggregated quality data. The method includes determining supplier quality level for the supplier for the supplier measurement time period. The supplier quality is based on the supplier quality data. The method includes determining if the supplier quality data exceeds an alarm level.

    摘要翻译： 确定质量的方法包括从供应商接收供应商质量数据。 供应商质量数据包括离散质量数据。 供应商的质量数据是供应商测量期间提供给公司或代表公司提供的服务的数量。 该方法包括汇总来自两个或更多供应商的质量数据。 质量数据用于提供的组件或在基准时间段内提供的服务。 该方法包括使用聚合质量数据确定质量基准并设置一个或多个警报级别。 报警水平基于聚合质量数据的质量基准。 该方法包括为供应商测量时间段确定供应商的供应商质量水平。 供应商质量是根据供应商的质量数据。 该方法包括确定供应商质量数据是否超过报警级别。

    Modifying a manufacturing process of integrated circuits based on large scale quality performance prediction and optimization
    10.
    发明授权
    Modifying a manufacturing process of integrated circuits based on large scale quality performance prediction and optimization 有权

    公开(公告)号：US10318700B2

    公开(公告)日：2019-06-11

    申请号：US15695071

    申请日：2017-09-05

    申请人： International Business Machines Corporation

    发明人： Steven B. Gold ,  Wen Wei Low ,  Feng Xue ,  Yvonne Chii Yeo ,  Jung H. Yoon

    IPC分类号： G06F17/50

    摘要： A computer-implemented method modifies a manufacturing process for integrated circuits. One or more processors receive sensor readings that identify failed integrated circuits from a batch of integrated circuits, where each of the integrated circuits includes a set of dynamic random access memory (DRAM) chips and a memory buffer, where the memory buffer provides an interface between a memory controller and the DRAM chips. The processor(s) identify, based on the sensor readings, a performance trending estimate of DRAM failures versus memory buffer failures in the identified failed integrated circuits. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, a location and address of each DRAM in the identified failed integrated circuits, and a wafer location on the wafer die on which each memory buffer that has the memory buffer failure, such that a manufacturing process for the integrated circuits is modified based on the FA pareto.