利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.025 秒)

    Creating a program product or system for executing an instruction for pre-fetching data and releasing cache lines
    1.
    发明授权
    Creating a program product or system for executing an instruction for pre-fetching data and releasing cache lines 有权
    创建用于执行预取数据和释放高速缓存行的指令的程序产品或系统

    公开(公告)号：US09069675B2

    公开(公告)日：2015-06-30

    申请号：US14221869

    申请日：2014-03-21

    申请人： International Business Machines Corporation

    发明人： Dan F Greiner ,  Timothy J Slegel

    IPC分类号： G06F12/08 ,  G06F9/30 ,  G06F9/38

    CPC分类号： G06F12/0862 ,  G06F9/30047 ,  G06F9/383 ,  G06F9/3832 ,  G06F2212/6028

    摘要： Systems and Program Products are created to execute a prefetch data machine instruction having an M field performs a function on a cache line of data specifying an address of an operand. The operation comprises either prefetching a cache line of data from memory to a cache or reducing the access ownership of store and fetch or fetch only of the cache line in the cache or a combination thereof. The address of the operand is either based on a register value or the program counter value pointing to the prefetch data machine instruction.

    摘要翻译： 创建系统和程序产品以执行具有M字段的预取数据机器指令，以在指定操作数的地址的数据的高速缓存行上执行功能。 该操作包括将来自存储器的数据的高速缓存行预取到高速缓存或减少对高速缓存中的存储和获取或仅获取高速缓存行的访问所有权或其组合。 操作数的地址是基于寄存器值或指向预取数据机器指令的程序计数器值。

    Creating a program product or system for executing a perform frame management instruction
    3.
    发明授权
    Creating a program product or system for executing a perform frame management instruction 有权
    创建用于执行执行帧管理指令的程序产品或系统

    公开(公告)号：US09158711B2

    公开(公告)日：2015-10-13

    申请号：US14561703

    申请日：2014-12-05

    申请人： International Business Machines Corporation

    发明人： Dan F Greiner ,  Charles W Gainey, Jr. ,  Lisa C Heller ,  Damian L Osisek ,  Timothy J Slegel ,  Gustav E Sittmann

    IPC分类号： G06F12/00 ,  G06F12/14 ,  G06F9/30 ,  G06F12/02 ,  G06F12/10

    CPC分类号： G06F12/1475 ,  G06F9/30003 ,  G06F9/3004 ,  G06F9/30145 ,  G06F12/00 ,  G06F12/023 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/145 ,  G06F2212/68

    摘要： Creating a computer program product or a computer system to execute a frame management instruction which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.

    摘要翻译： 创建计算机程序产品或计算机系统以执行标识第一和第二通用寄存器的帧管理指令。 第一通用寄存器包含具有带有访问保护位的密钥字段和块大小指示的帧管理字段。 如果块大小指示指示大块，则从第二通用寄存器获得大数据块的操作数地址。 大块数据具有多个小块，每个小块与具有多个存储密钥访问保护位的对应存储密钥相关联。 如果块大小指示指示大块，则使用密钥字段的访问保护位来设置大块内的每个小块的每个相应的存储密钥的存储密钥访问保护位。

    Load pair disjoint facility and instruction therefor
    4.
    发明授权
    Load pair disjoint facility and instruction therefor 有权
    负载对不相交的设施和指令

    公开(公告)号：US09052889B2

    公开(公告)日：2015-06-09

    申请号：US13726746

    申请日：2012-12-26

    申请人： International Business Machines Corporation

    发明人： Christian Jacobi ,  Marcel Mitran ,  Timothy J Slegel ,  Charles F Webb

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/30043 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3834

    摘要： A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers.

    摘要翻译： 加载/存储不相交指令在由CPU执行时，从两个不相交的存储器位置访问操作数，并设置条件代码指示符，以指示两个操作数是否似乎以原子方式访问，通过块并发互锁获取，无中间存储 到其他CPU的操作数。 在负载对不相交形式的指令中，访问是加载，不相交的数据存储在通用寄存器中。

    Emulating execution of a perform frame management instruction
    8.
    发明授权
    Emulating execution of a perform frame management instruction 有权
    仿真执行执行帧管理指令

    公开(公告)号：US08909899B2

    公开(公告)日：2014-12-09

    申请号：US13928807

    申请日：2013-06-27

    申请人： International Business Machines Corporation

    发明人： Dan F Greiner ,  Charles W Gainey, Jr. ,  Lisa C Heller ,  Damian L Osisek ,  Timothy J Slegel ,  Gustav E Sittmann

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1475 ,  G06F9/30003 ,  G06F9/3004 ,  G06F9/30145 ,  G06F12/00 ,  G06F12/023 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/145 ,  G06F2212/68

    摘要： What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.

    摘要翻译： 公开的是针对计算机系统的机器结构定义的帧管理功能。 在一个实施例中，获得识别第一和第二通用寄存器的帧管理指令。 第一通用寄存器包含具有带有访问保护位的密钥字段和块大小指示的帧管理字段。 如果块大小指示指示大块，则从第二通用寄存器获得大数据块的操作数地址。 大块数据具有多个小块，每个小块与具有多个存储密钥访问保护位的对应存储密钥相关联。 如果块大小指示指示大块，则使用密钥字段的访问保护位来设置大块内的每个小块的每个相应的存储密钥的存储密钥访问保护位。