公开(公告)号：US20060237784A1

公开(公告)日：2006-10-26

申请号：US11114455

申请日：2005-04-25

申请人： Irfan Rahim ,  Yow-Juang Liu ,  Jeffrey Watt

发明人： Irfan Rahim ,  Yow-Juang Liu ,  Jeffrey Watt

IPC分类号： H01L29/76

CPC分类号： H01L27/0203 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/11807 ,  H01L27/11898 ,  Y10S257/903

摘要： An integrated circuit having an enhanced on-off swing for pass gate transistors is provided. The integrated circuit includes a core region that includes core transistors and pass gate transistors. The core transistors have a gate oxide associated with a first thickness, the pass transistors having a gate oxide associated with a thickness that is less than the first thickness. In one embodiment, the material used for the gate oxide of the pass gate transistors has a dielectric constant that is greater than four, while the material used for the gate oxide of the core transistors has a dielectric constant that is less than or equal to four. A method for manufacturing an integrated circuit is also provided.

摘要翻译： 提供了一种具有用于通过栅极晶体管的增强的通断摆幅的集成电路。 集成电路包括具有核心晶体管和栅极晶体管的核心区域。 核心晶体管具有与第一厚度相关的栅极氧化物，所述通过晶体管具有与小于第一厚度的厚度相关联的栅极氧化物。 在一个实施例中，用于栅极晶体管的栅极氧化物的材料具有大于4的介电常数，而用于核心晶体管的栅极氧化物的材料具有小于或等于4的介电常数 。 还提供了一种用于制造集成电路的方法。

公开(公告)号：US20060001045A1

公开(公告)日：2006-01-05

申请号：US10883091

申请日：2004-07-01

申请人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

发明人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

IPC分类号： H01L29/739 ,  H01L27/10 ,  G11C16/04 ,  G11C11/34

CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11807

摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

摘要翻译： 用于现场可编程门阵列（“FPGA”）集成电路（“IC”）器件的配置存储单元（“CRAM”）被赋予增加的对单一事件不正常（“SEU”）的阻力。 CRAM的输入节点的栅极结构的一部分相对于栅极结构的其余部分的标称尺寸增大。 放大栅极结构的一部分位于与IC的N阱区电容性相邻的位置，另一部分位于与IC的P阱区电容相邻的位置。 这种布置使得输入节点增加了抵抗SEU的电容，而与输入节点的逻辑电平无关。 本发明也可应用于任何类型的存储器单元的任何节点，其对期望增加的对SEU的抗性。

公开(公告)号：US20070132482A1

公开(公告)日：2007-06-14

申请号：US11672444

申请日：2007-02-07

申请人： Irfan Rahim ,  Jeffrey Watt

发明人： Irfan Rahim ,  Jeffrey Watt

IPC分类号： H03K19/173

CPC分类号： H03K19/0027 ,  H03K2217/0018

摘要： Apparatus and methods are disclosed for improving the performance of a programmable logic device (PLD). A PLD includes a memory cell configured to provide a pair of voltages to a gate of a pass transistor and a body of the pass transistor, respectively.

摘要翻译： 公开了用于改善可编程逻辑器件（PLD）的性能的装置和方法。 PLD包括被配置为分别向传输晶体管的栅极和传输晶体管的主体提供一对电压的存储单元。

公开(公告)号：US07465971B2

公开(公告)日：2008-12-16

申请号：US11951122

申请日：2007-12-05

申请人： Lakhbeer S. Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

发明人： Lakhbeer S. Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

IPC分类号： H01L29/94

CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11807

摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

公开(公告)号：US07361961B2

公开(公告)日：2008-04-22

申请号：US11114455

申请日：2005-04-25

申请人： Irfan Rahim ,  Yow-Juang Bill Liu ,  Jeffrey Watt

发明人： Irfan Rahim ,  Yow-Juang Bill Liu ,  Jeffrey Watt

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/0203 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/11807 ,  H01L27/11898 ,  Y10S257/903

摘要： An integrated circuit having an enhanced on-off swing for pass gate transistors is provided. The integrated circuit includes a core region that includes core transistors and pass gate transistors. The core transistors have a gate oxide associated with a first thickness, the pass transistors having a gate oxide associated with a thickness that is less than the first thickness. In one embodiment, the material used for the gate oxide of the pass gate transistors has a dielectric constant that is greater than four, while the material used for the gate oxide of the core transistors has a dielectric constant that is less than or equal to four. A method for manufacturing an integrated circuit is also provided.

摘要翻译： 提供了一种具有用于通过栅极晶体管的增强的通断摆幅的集成电路。 集成电路包括具有核心晶体管和栅极晶体管的核心区域。 核心晶体管具有与第一厚度相关的栅极氧化物，所述通过晶体管具有与小于第一厚度的厚度相关联的栅极氧化物。 在一个实施例中，用于栅极晶体管的栅极氧化物的材料具有大于4的介电常数，而用于核心晶体管的栅极氧化物的材料具有小于或等于4的介电常数 。 还提供了一种用于制造集成电路的方法。

公开(公告)号：US20080074145A1

公开(公告)日：2008-03-27

申请号：US11951122

申请日：2007-12-05

申请人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

发明人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

IPC分类号： H03K19/173

CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11807

摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

摘要翻译： 用于现场可编程门阵列（“FPGA”）集成电路（“IC”）器件的配置存储单元（“CRAM”）被赋予增加的对单一事件不正常（“SEU”）的阻力。 CRAM的输入节点的栅极结构的一部分相对于栅极结构的其余部分的标称尺寸增大。 放大栅极结构的一部分位于与IC的N阱区电容性相邻的位置，另一部分位于与IC的P阱区电容相邻的位置。 这种布置使得输入节点增加了抵抗SEU的电容，而与输入节点的逻辑电平无关。 本发明也可应用于任何类型的存储器单元的任何节点，其对期望增加的对SEU的抗性。

公开(公告)号：US07142009B1

公开(公告)日：2006-11-28

申请号：US10942692

申请日：2004-09-15

申请人： Jeffrey Watt ,  Irfan Rahim

发明人： Jeffrey Watt ,  Irfan Rahim

IPC分类号： H03K19/173 ,  G06F1/26

CPC分类号： H03K19/0008 ,  H03K19/177

摘要： Adaptive regulated power supply voltages are applied to programmable logic integrated circuits. Control circuitry in a programmable logic IC generates control signals that are transmitted to an external voltage regulator. The voltage regulator generates one or more power supply voltages in response to the control signals. The values of control signals determine the target values of the supply voltages. The control circuitry can adapt the power supply voltages to compensate for temperature and process variations on the IC. The power supply voltages can be programmed by a manufacturer or by a user to achieve desired target values. The control circuitry can also put a programmable logic IC into a sleep mode by dropping the high supply voltage to a low value to reduce power consumption during periods of low usage.

摘要翻译： 自适应稳压电源电压被施加到可编程逻辑集成电路。 可编程逻辑IC中的控制电路产生传输到外部电压调节器的控制信号。 电压调节器响应于控制信号产生一个或多个电源电压。 控制信号的值确定电源电压的目标值。 控制电路可以调节电源电压以补偿IC上的温度和工艺变化。 电源电压可以由制造商或用户编程以实现期望的目标值。 控制电路还可以通过将高电源电压降低到低值来将可编程逻辑IC置于睡眠模式，以在低使用期间降低功耗。

公开(公告)号：US07858469B1

公开(公告)日：2010-12-28

申请号：US12565855

申请日：2009-09-24

申请人： Jeffrey Watt ,  Irfan Rahim

发明人： Jeffrey Watt ,  Irfan Rahim

IPC分类号： H01L21/8234

CPC分类号： H01L27/0262 ,  H01L29/4983 ,  H01L29/66659 ,  H01L29/7835

摘要： The present invention is a trigger device useful, for example, in triggering an SCR in an ESD protection circuit. Illustratively, an NMOS trigger device comprises a gate and heavily doped P and N regions in a P-well on opposite sides of the gate. A first N type source/drain extension and a first P-type pocket region extend from the P region toward the N region with the pocket region located under the source/drain extension and extending under the gate. A second N-type source/drain extension and a second P-type pocket region extend from the N region toward the P region with the pocket region located under the source/drain extension and extending under the gate. Preferably, the gate itself is heavily doped so that one half of the gate on the side adjacent the heavily doped P region is also heavily doped with dopants of P-type conductivity and the other half of the gate on the side adjacent the heavily doped N region is also heavily doped with dopants of N-type conductivity. Doping the gate increases the threshold voltage by about one Volt due to an increase in the work function on the source side of the gate.

摘要翻译： 本发明是一种触发装置，例如用于触发ESD保护电路中的SCR。 说明性地，NMOS触发器件包括在栅极的相对侧上的P阱中的栅极和重掺杂P和N区。 第一N型源极/漏极延伸部分和第一P型凹槽区域从P区域朝向N区域延伸，其中凹部区域位于源极/漏极延伸部下方并在栅极下方延伸。 第二N型源极/漏极延伸部分和第二P型凹槽区域从N区域延伸到P区域，其中该凹陷区域位于源极/漏极延伸部分下方并在栅极之下延伸。 优选地，栅极本身是重掺杂的，使得与重掺杂P区相邻的一侧的栅极的一半也被P型导电性的掺杂剂重掺杂，并且与重掺杂N相邻的一侧栅极的另一半 区域也被N型导电性的掺杂剂重掺杂。 由于栅极的源极侧的功函数增加，掺杂栅极将阈值电压提高约1伏特。

公开(公告)号：US07612410B1

公开(公告)日：2009-11-03

申请号：US11199614

申请日：2005-08-08

申请人： Jeffrey Watt ,  Irfan Rahim

发明人： Jeffrey Watt ,  Irfan Rahim

IPC分类号： H01L29/861

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： The present invention is a trigger device useful, for example, in triggering an SCR in an ESD protection circuit. Illustratively, an NMOS trigger device comprises a gate and heavily doped P and N regions in a P-well on opposite sides of the gate. A first N type source/drain extension and a first P-type pocket region extend from the P region toward the N region with the pocket region located under the source/drain extension and extending under the gate. A second N-type source/drain extension and a second P-type pocket region extend from the N region toward the P region with the pocket region located under the source/drain extension and extending under the gate. Preferably, the gate itself is heavily doped so that one half of the gate on the side adjacent the heavily doped P region is also heavily doped with dopants of P-type conductivity and the other half of the gate on the side adjacent the heavily doped N region is also heavily doped with dopants of N-type conductivity. Doping the gate increases the threshold voltage by about one Volt due to an increase in the work function on the source side of the gate.

摘要翻译： 本发明是一种触发装置，例如用于触发ESD保护电路中的SCR。 说明性地，NMOS触发器件包括在栅极的相对侧上的P阱中的栅极和重掺杂P和N区。 第一N型源极/漏极延伸部分和第一P型凹槽区域从P区域朝向N区域延伸，其中凹部区域位于源极/漏极延伸部下方并在栅极下方延伸。 第二N型源极/漏极延伸部分和第二P型凹槽区域从N区域延伸到P区域，其中该凹陷区域位于源极/漏极延伸部分下方并在栅极之下延伸。 优选地，栅极本身是重掺杂的，使得与重掺杂P区相邻的一侧的栅极的一半也被P型导电性的掺杂剂重掺杂，并且与重掺杂N相邻的一侧栅极的另一半 区域也被N型导电性的掺杂剂重掺杂。 由于栅极的源极侧的功函数增加，掺杂栅极将阈值电压提高约1伏特。

公开(公告)号：US07319253B2

公开(公告)日：2008-01-15

申请号：US10883091

申请日：2004-07-01

申请人： Lakhbeer S Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John E Turner

发明人： Lakhbeer S Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John E Turner

IPC分类号： H01L27/108

CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11807

摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

摘要翻译： 用于现场可编程门阵列（“FPGA”）集成电路（“IC”）器件的配置存储单元（“CRAM”）被赋予增加的对单一事件不正常（“SEU”）的阻力。 CRAM的输入节点的栅极结构的一部分相对于栅极结构的其余部分的标称尺寸增大。 放大栅极结构的一部分位于与IC的N阱区电容性相邻的位置，另一部分位于与IC的P阱区电容相邻的位置。 这种布置使得输入节点增加了抵抗SEU的电容，而与输入节点的逻辑电平无关。 本发明也可应用于任何类型的存储器单元的任何节点，其对期望增加的对SEU的抗性。