-
1.发明申请公开(公告)号：US20090031053A1
公开(公告)日：2009-01-29
申请号：US12172512
申请日：2008-07-14
申请人： Itaru Nonomura , Makoto Saen , Kenichi Osada
发明人： Itaru Nonomura , Makoto Saen , Kenichi Osada
CPC分类号： G06F13/4045 , H01L2924/0002 , H01L2924/00
摘要： An interconnect configuration technology of making an access from an IP mounted on a semiconductor chip to an IP mounted on another semiconductor chip by transmitting and receiving a packet transferred through an interconnect built in a semiconductor chip among the chips using the 3D coupling technology. The device according to the technology has an initiator for transmitting an access request, a target for receiving the access request and transmitting an access response, a router for relaying the access request and the access response, and a 3D coupling circuit (three-dimensional transceiver) for performing communication with the outside, wherein the 3D coupling circuit is disposed adjacent to the router.
摘要翻译： 一种互连配置技术，其通过使用3D耦合技术发送和接收通过内置在半导体芯片中的互连的芯片传输的分组，从安装在半导体芯片上的IP到安装在另一半导体芯片上的IP进行访问。 根据该技术的设备具有用于发送接入请求的发起者，用于接收接入请求并发送接入响应的目标，用于中继接入请求和接入响应的路由器，以及3D耦合电路（三维收发机 ），用于与外部进行通信，其中所述3D耦合电路邻近所述路由器设置。
-
公开(公告)号：US08054871B2
公开(公告)日：2011-11-08
申请号：US12370338
申请日：2009-02-12
CPC分类号： H01L25/0657 , H01L24/16 , H01L2224/16 , H01L2225/06517 , H01L2225/06527 , H01L2924/14 , H01L2924/15311 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107
摘要： A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.
摘要翻译： 一种半导体器件，包括能够通过无线彼此通信的一对叠层半导体IC。 每个IC具有：发射机电路，其可操作来通过无线发送数据与决定发送定时的时钟信号一起发送，并且被布置成使得无线发送定时是可调节的; 接收机电路，可操作以与由无线接收的时钟信号同步地接收数据，并且被布置为使得其无线接收定时是可调节的; 以及控制电路，其可操作以基于由所述另一IC响应于通过所述发射机电路发送的数据并由所述接收机电路接收的数据的认证的结果执行所述发射机和接收机电路的定时调整。 用于层叠半导体IC之间的近场通信的这种布置使得能够减少用于通信定时调整的电路的规模; 并高度准确地调整通讯时机。
-
公开(公告)号：US07994623B2
公开(公告)日：2011-08-09
申请号：US12167228
申请日：2008-07-02
申请人： Itaru Nonomura , Kenichi Osada , Makoto Saen
发明人： Itaru Nonomura , Kenichi Osada , Makoto Saen
CPC分类号： H01L25/0657 , H01L23/48 , H01L24/06 , H01L24/48 , H01L24/73 , H01L25/18 , H01L2224/0401 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01047 , H01L2924/01055 , H01L2924/01075 , H01L2924/01082 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device where multiple chips of identical design can be stacked, and the spacer and interposer eliminated, to improve three-dimensional coupling information transmission capability. A first semiconductor circuit including a three-dimensional coupling circuit (three-dimensional coupling transmission terminal group and three-dimensional coupling receiver terminal group); and a second semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode (power supply via hole and ground via hole); and a third semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode are stacked on the package substrate.
摘要翻译： 可以堆叠具有相同设计的多个芯片的半导体器件，并且消除间隔件和插入件，以改善三维耦合信息传输能力。 包括三维耦合电路（三维耦合传输端子组和三维耦合接收器端子组）的第一半导体电路; 以及包括三维耦合电路和馈通电极（电源通孔和接地通孔）的第二半导体集成电路; 并且在封装衬底上堆叠包括三维耦合电路和馈通电极的第三半导体集成电路。
-
公开(公告)号：US07849237B2
公开(公告)日：2010-12-07
申请号：US12172512
申请日：2008-07-14
申请人： Itaru Nonomura , Makoto Saen , Kenichi Osada
发明人： Itaru Nonomura , Makoto Saen , Kenichi Osada
IPC分类号： G06F13/12
CPC分类号： G06F13/4045 , H01L2924/0002 , H01L2924/00
摘要： An interconnect configuration technology of making an access from an IP mounted on a semiconductor chip to an IP mounted on another semiconductor chip by transmitting and receiving a packet transferred through an interconnect built in a semiconductor chip among the chips using the 3D coupling technology. The device according to the technology has an initiator for transmitting an access request, a target for receiving the access request and transmitting an access response, a router for relaying the access request and the access response, and a 3D coupling circuit (three-dimensional transceiver) for performing communication with the outside, wherein the 3D coupling circuit is disposed adjacent to the router.
摘要翻译： 一种互连配置技术，其通过使用3D耦合技术发送和接收通过内置在半导体芯片中的互连的芯片传输的分组，从安装在半导体芯片上的IP到安装在另一半导体芯片上的IP进行访问。 根据该技术的设备具有用于发送接入请求的发起者，用于接收接入请求并发送接入响应的目标，用于中继接入请求和接入响应的路由器，以及3D耦合电路（三维收发机 ），用于与外部进行通信，其中所述3D耦合电路邻近所述路由器设置。
-
公开(公告)号：US20090245445A1
公开(公告)日：2009-10-01
申请号：US12370338
申请日：2009-02-12
IPC分类号： H04L7/00
CPC分类号： H01L25/0657 , H01L24/16 , H01L2224/16 , H01L2225/06517 , H01L2225/06527 , H01L2924/14 , H01L2924/15311 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107
摘要： A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.
摘要翻译： 一种半导体器件，包括能够通过无线彼此通信的一对叠层半导体IC。 每个IC具有：发射机电路，其可操作来通过无线发送数据与决定发送定时的时钟信号一起发送，并且被布置成使得无线发送定时是可调节的; 接收机电路，可操作以与由无线接收的时钟信号同步地接收数据，并且被布置为使得其无线接收定时是可调节的; 以及控制电路，其可操作以基于由所述另一IC响应于通过所述发射机电路发送的数据并由所述接收机电路接收的数据的认证的结果执行所述发射机和接收机电路的定时调整。 用于层叠半导体IC之间的近场通信的这种布置使得能够减少用于通信定时调整的电路的规模; 并高度准确地调整通讯时机。
-
公开(公告)号：US06727907B2
公开(公告)日：2004-04-27
申请号：US10086832
申请日：2002-03-04
IPC分类号： G09G502
CPC分类号： G06F3/14 , G09G2340/0414 , G09G2340/0421 , G09G2340/12 , H04N5/4401 , H04N5/445 , H04N7/088 , H04N9/641 , H04N21/4135 , H04N21/4143 , H04N21/4355 , H04N21/4884
摘要： A video data display board, device or method for inputting and displaying video data including vertical blanking interval data containing character data and other image data than the vertical blanking interval data. The video data display device has a data transfer circuit capable of transferring both of the data to devices different from each other, so that the processing of character information and image data are performed by using the different devices which perform an appropriate process according to the property of the data. The processed character and image data are displayed on a graphic display screen simultaneously.
摘要翻译： 视频数据显示板，用于输入和显示包括垂直消隐间隔数据的视频数据的装置或方法，所述垂直消隐间隔数据包含与垂直消隐间隔数据相比的字符数据和其他图像数据。 视频数据显示装置具有数据传输电路，能够将数据传送到彼此不同的装置，从而通过使用根据属性执行适当处理的不同装置来执行字符信息和图像数据的处理 的数据。 处理的字符和图像数据同时显示在图形显示屏幕上。
-
公开(公告)号：US08531893B2
公开(公告)日：2013-09-10
申请号：US13674043
申请日：2012-11-11
IPC分类号： G11C7/10
CPC分类号： G06F1/3253 , G06F1/3237 , Y02D10/128 , Y02D10/151
摘要： In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
摘要翻译： 在具有总线控制器的数据处理器中，总线控制器执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，提供定时控制电路 在外围电路和总线控制器之间，并且总线控制器响应于来自外围电路的读取指令而导致定时控制电路将周边电路保持的数据与高速的周期同步地传送到总线控制器 速度时钟信号，使定时控制电路响应于指向外围电路的写指令而启动，与高速时钟信号的周期同步地写入外围电路，并且与 低速时钟信号的周期。
-
公开(公告)号：US08339869B2
公开(公告)日：2012-12-25
申请号：US13220747
申请日：2011-08-30
CPC分类号： G06F1/3253 , G06F1/3237 , Y02D10/128 , Y02D10/151
摘要： To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
摘要翻译： 提高从高速电路块访问低速电路块的速度，而不会显着增加功耗。 在具有总线控制器的数据处理器中，总线控制器执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，提供定时控制电路 在外围电路和总线控制器之间，并且总线控制器响应于来自外围电路的读取指令而导致定时控制电路将周边电路保持的数据与高速的周期同步地传送到总线控制器 速度时钟信号，使定时控制电路响应于指向外围电路的写指令而启动，与高速时钟信号的周期同步地写入外围电路，并且与 低速时钟信号的周期。
-
公开(公告)号：US20060174052A1
公开(公告)日：2006-08-03
申请号：US11047670
申请日：2005-02-02
申请人： Nobukazu Kondo , Kei Suzuki , Kouki Noguchi , Itaru Nonomura
发明人： Nobukazu Kondo , Kei Suzuki , Kouki Noguchi , Itaru Nonomura
IPC分类号： G06F13/00
CPC分类号： G06F13/4059
摘要： In an LSI system using an on-chip bus, when a transfer on the bus is delayed due to a fully loaded buffer in a destination module, a source module cannot proceed to the next processing. Such an unwanted situation is eliminated by a transferring buffer which is provided on a transfer path in an on-chip bus on the LSI for temporarily storing transfer data. With this transferring buffer, even if a buffer within a slave module, specified as the destination, is fully loaded and cannot accept any more transfer, a bus master can transfer data to the transferring buffer provided on the on-chip bus. Thus, the bus master is not kept waiting for execution of a transfer, irrespective of the state of the buffer within the slave, thereby improving the processing performance of the entire system.
摘要翻译： 在使用片上总线的LSI系统中，当总线上的传输由于目的地模块中的满载缓冲器而被延迟时，源模块不能进行下一个处理。 通过在LSI上的片上总线的传送路径上提供的用于临时存储传送数据的传送缓冲器来消除这种不希望的情况。 使用此传输缓冲区，即使指定为目标的从模块中的缓冲区已完全加载，也不能接受任何更多传输，总线主机可将数据传输到片上总线上提供的传输缓冲区。 因此，无论总线主机中的缓冲器的状态如何，总线主机不会等待执行转移，从而提高整个系统的处理性能。
-
公开(公告)号：US06675224B1
公开(公告)日：2004-01-06
申请号：US09500073
申请日：2000-02-08
申请人： Isao Takita , Naoko Iwami , Yoshiaki Eguchi , Shinichi Sawamura , Itaru Nonomura , Toru Owada , Yasushi Nagai , Shinichi Kato
发明人： Isao Takita , Naoko Iwami , Yoshiaki Eguchi , Shinichi Sawamura , Itaru Nonomura , Toru Owada , Yasushi Nagai , Shinichi Kato
IPC分类号： G06F15173
CPC分类号： G06F13/4072 , G06F13/385
摘要： A system which serves both as a host and a device cannot be realized with a single connector due to the constitution of hardware in the prior art. The prior art system only detects the existence of a device and cannot distinguish between a host and a device while a power source is turned on and switch its function. The information processing apparatus of the present invention separates the data lines of a host communication controller and the data lines of a device communication controller and activates the selected controller by means of selecting the data lines of the controllers and means of determining which is connected to a connector, a host or a device.
摘要翻译： 由于现有技术中的硬件的构成，用作主机和设备的系统不能用单个连接器来实现。 现有技术的系统仅检测设备的存在，并且在电源接通并切换其功能时不能区分主机和设备。 本发明的信息处理装置将主机通信控制器的数据线和设备通信控制器的数据线分开，并通过选择控制器的数据线和确定哪个连接到控制器的数据线来激活所选择的控制器 连接器，主机或设备。
-
-
-
-
-
-
-
-
-
搜索结果
22 条记录 (耗时 0.021 秒)
