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公开(公告)号：US20140003145A1
公开(公告)日：2014-01-02
申请号：US13537553
申请日：2012-06-29
CPC分类号： G06F3/0625 , G06F1/3287 , G06F3/0655 , G06F3/0688 , G06F11/1417 , G11C5/148 , G11C7/1072 , G11C14/0009 , Y02D10/171
摘要： Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.
摘要翻译： 利用包括一个或多个非易失性存储器件和易失性存储器系统的存储器子系统来利用非常低功率状态的技术。 存储器控制器与一个或多个非易失性存储器件和易失性存储器系统耦合。 存储器控制器至少包括嵌入式控制代理和存储状态信息的存储器位置。 存储器控制器，用于选择性地启用和禁用一个或多个非易失性存储器件。 存储器控制器在进入低功率状态之前将状态信息传送到易失性存储器系统。 控制电路与存储器控制器耦合。 所述控制电路用于选择性地启用和禁用所述存储器控制器的操作。
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公开(公告)号：US20150277930A1
公开(公告)日：2015-10-01
申请号：US14229708
申请日：2014-03-28
CPC分类号： G06F21/572 , G06F9/4403 , G06F9/4406 , G06F9/4411 , G06F11/1417 , G06F21/57 , G06F21/575 , G06F2212/1052 , G06F2221/03 , G06F2221/033
摘要： A hardware platform includes a nonvolatile storage device that can store system firmware as well as code for the primary operating system for the hardware platform. The hardware platform includes a controller that determines the hardware platform lacks functional firmware to boot the primary operating system from the storage device. The controller accesses a firmware image from an external interface that interfaces a device external to the hardware platform, where the external device is a firmware image source. The controller provisions the firmware from the external device to the storage device and initiates a boot sequence from the provisioned firmware.
摘要翻译： 硬件平台包括可以存储系统固件的非易失性存储设备以及用于硬件平台的主操作系统的代码。 硬件平台包括一个确定硬件平台的控制器缺乏从存储设备引导主操作系统的功能固件。 控制器从外部接口访问固件映像，该外部接口将硬件平台外部的设备连接到外部设备是固件映像源。 控制器将固件从外部设备提供给存储设备，并从配置的固件启动启动顺序。
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公开(公告)号：US20100169710A1
公开(公告)日：2010-07-01
申请号：US12345997
申请日：2008-12-30
CPC分类号： G06F11/1441 , G06F12/0246 , G06F2212/7207 , Y02D10/13
摘要： According to some embodiments, delta checkpoints are provided for a non-volatile memory indirection table to facilitate a recovery process after a power loss event.
摘要翻译： 根据一些实施例，为非易失性存储器间接表提供增量检查点，以便于在功率损失事件之后恢复过程。
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公开(公告)号：US20140115315A1
公开(公告)日：2014-04-24
申请号：US13977081
申请日：2011-12-27
IPC分类号： G06F9/44
CPC分类号： G06F9/4403 , G06F3/0601 , G06F9/4401 , G06F12/10 , Y02D10/13
摘要： Various embodiments are directed to apparatuses and methods for faster solid state drive (SSD) boot-up. On boot-up, SSD control algorithms may load non-logical to physical (L2P) parts of a context and signal the system that the SSD is ready. The context may comprise various state data pertaining to the SSD. After signaling that the SSD may be ready to receive access requests, the SSD control algorithms may begin loading segments of the L2P table sequentially. Access to the L2P table may be blocked, however, when a requested segment has not yet been loaded. In such cases, the SSD control algorithms may then load the requested segment out of turn and then service the access request.
摘要翻译： 各种实施例涉及用于更快的固态驱动（SSD）启动的装置和方法。 在启动时，SSD控制算法可以将非逻辑加载到上下文的物理（L2P）部分，并向系统通知SSD已准备就绪。 上下文可以包括与SSD相关的各种状态数据。 在指示SSD可能准备好接收访问请求之后，SSD控制算法可以开始依次加载L2P表的段。 但是，当请求的段尚未加载时，可能会阻止对L2P表的访问。 在这种情况下，SSD控制算法可以随后加载所请求的段，然后服务于访问请求。
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公开(公告)号：US20100332730A1
公开(公告)日：2010-12-30
申请号：US12495573
申请日：2009-06-30
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7207
摘要： A method and system to facilitate paging of one or more segments of a logical-to-physical (LTP) address mapping structure to a non-volatile memory. The LTP address mapping structure is part of an indirection system map associated with the non-volatile memory in one embodiment of the invention. By allowing one or more segments of the LTP address mapping structure to be paged to the non-volatile memory, the amount of volatile memory required to store the LTP address mapping structure is reduced while maintaining the benefits of the LTP address mapping structure in one embodiment of the invention.
摘要翻译： 一种有助于将逻辑到物理（LTP）地址映射结构的一个或多个段分页到非易失性存储器的方法和系统。 在本发明的一个实施例中，LTP地址映射结构是与非易失性存储器相关联的间接系统映射的一部分。 通过允许LTP地址映射结构的一个或多个段被分页到非易失性存储器，在一个实施例中保持LTP地址映射结构的优点的同时，减少存储LTP地址映射结构所需的易失性存储器的量 的本发明。
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公开(公告)号：US20150095563A1
公开(公告)日：2015-04-02
申请号：US14039129
申请日：2013-09-27
申请人： Robert J. Royer, JR.
发明人： Robert J. Royer, JR.
IPC分类号： G06F12/06
CPC分类号： G06F3/0604 , G06F3/06 , G06F3/064 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F12/0238 , G06F2212/202 , G06F2212/7201 , G06F2212/7204
摘要： Apparatus, systems, and methods to manage memory operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to retrieve a global sequence number from a memory device, receive a read request for data stored in a logical block address in the memory device, retrieve a media sequence number from the logical block address in the memory device, and return a null response in lieu of the data stored in the logical block address when the media sequence number is older than the global sequence number. Other embodiments are also disclosed and claimed.
摘要翻译： 描述了管理存储器操作的装置，系统和方法。 在一个实施例中，电子设备包括处理器和存储器控制逻辑以从存储器设备检索全局序列号，接收对存储在存储器设备中的逻辑块地址中的数据的读取请求，从存储器设备中检索媒体序列号 逻辑块地址，并且当媒体序列号比全局序列号更早时，返回空响应代替存储在逻辑块地址中的数据。 还公开并要求保护其他实施例。
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公开(公告)号：US20150032941A1
公开(公告)日：2015-01-29
申请号：US14128669
申请日：2013-07-25
申请人： Eng Hun Ooi , Robert J. Royer, JR. , Michael W. Williams , Jeffrey R. Wilcox , Ritesh B. Trivedi , Blaise Fanning
发明人： Eng Hun Ooi , Robert J. Royer, JR. , Michael W. Williams , Jeffrey R. Wilcox , Ritesh B. Trivedi , Blaise Fanning
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0679 , G06F12/02 , G06F13/12 , G06F13/16 , G06F13/1668 , G06F13/38 , G06F13/4234 , G06F2212/7202
摘要： In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.
摘要翻译： 在一个实施例中，存储器接口可以发送请求被发送的指示。 该指示可以经由存储器接口和非易失性存储器之间的点对点总线发送到非易失性存储器。 存储器接口可以经由总线将请求发送到非易失性存储器。 请求可以包括可用于标识用于存储或读取数据的位置的地址。 非易失性存储器可以从总线获取请求并处理请求。 在处理请求之后，非易失性存储器可以向存储器接口发送指示非易失性存储器具有发送到存储器接口的响应的指示。 存储器接口可以向总线授予对非易失性存储器的访问。 在被允许访问总线之后，非易失性存储器可以将响应发送到存储器接口。
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公开(公告)号：US20110238918A1
公开(公告)日：2011-09-29
申请号：US13074870
申请日：2011-03-29
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F11/1417 , G06F11/1471 , G06F12/0802
摘要： An apparatus, as well as systems, methods, and articles can operate to record the address of write operations to a memory cached by a non-volatile cache prior to executing an operating system cache driver. In an embodiment, a non-volatile cache may be implemented by creating a device option read only memory (ROM), or modifying the associated computer basic input-output system (BIOS) to trap software interrupts associated with disk and other media access requests. Associated addresses, such as logical block addresses, can be stored in a log for data that is modified. The resulting log can be stored in a non-volatile medium, including the cache itself. If the available log space is not large enough to record all write activity prior to loading operating system drivers, a flag may be set to indicate the overrun condition.
摘要翻译： 在执行操作系统高速缓存驱动器之前，设备以及系统，方法和文章可以操作以将写入操作的地址记录到由非易失性高速缓存的存储器中。 在一个实施例中，可以通过创建设备选项只读存储器（ROM）或修改相关联的计算机基本输入 - 输出系统（BIOS）来捕获与磁盘和其他媒体访问请求相关联的软件中断来实现非易失性高速缓存。 关联的地址，例如逻辑块地址，可以存储在修改的数据的日志中。 所得到的日志可以存储在非易失性介质中，包括缓存本身。 如果可用的日志空间不足以在加载操作系统驱动程序之前记录所有写入活动，则可以设置一个标志来指示超限状态。
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公开(公告)号：US20140019676A1
公开(公告)日：2014-01-16
申请号：US14024724
申请日：2013-09-12
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G11C16/10 , G11C16/32
摘要： A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.
摘要翻译： 控制诸如NAND存储设备的闪存设备的系统和方法可以包括接收执行操作的命令。 响应于确定操作的执行已经完成，存储器件的就绪/忙触点可以被脉冲为低脉冲。
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公开(公告)号：US20120173794A1
公开(公告)日：2012-07-05
申请号：US12984723
申请日：2011-01-05
IPC分类号： G06F12/00
CPC分类号： G06F11/1456 , G06F11/1451 , G06F11/1469
摘要： Systems and methods of managing computing system restore points may include an apparatus having logic to receive a command to start a restore point for a solid state drive (SSD). The logic may also conduct a context drop of an indirection table from a volatile memory of the SSD to a non-volatile memory of the SSD in response to the command to start the restore point.
摘要翻译： 管理计算系统还原点的系统和方法可以包括具有接收用于启动固态驱动器（SSD）的还原点的命令的逻辑的装置。 响应于启动还原点的命令，该逻辑还可以将间接表的上下文下降从SSD的易失性存储器进行到SSD的非易失性存储器。
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