公开(公告)号：US07826267B2

公开(公告)日：2010-11-02

申请号：US12126853

申请日：2008-05-23

申请人： Jack Frayer ,  Ya-Fen Lin ,  Gianfranco Pellegrini ,  William Saiki ,  Changyuan Chen ,  Xiuhong Chen

发明人： Jack Frayer ,  Ya-Fen Lin ,  Gianfranco Pellegrini ,  William Saiki ,  Changyuan Chen ,  Xiuhong Chen

IPC分类号： G11C16/06

CPC分类号： G11C16/0475 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0458 ,  G11C16/0491 ,  G11C2211/5612

摘要： A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged voltage. One of the first or second global bit lines is connected to a low voltage such as ground, wherein the one global bit line connected to ground also connects to the local bit line for sensing the select non-volatile memory cell. The state of the select non-volatile memory cell is detected by detecting the sense amplifier connected to the global bit line, other than the one global bit line. In a dynamic programming operation, the first and second global bit lines and their associated local bit lines are precharged to a first voltage. One of the first or second global bit line and its associated local bit lines is connected to a second voltage.

摘要翻译： 公开了一种用于虚拟接地阵列中的选择非易失性存储单元的动态编程和动态读取的方法和装置。 在动态读取操作中，全局位线和相关联的局部位线连接到预充电电压。 第一或第二全局位线中的一个连接到诸如地的低电压，其中连接到地的一个全局位线还连接到本地位线以感测选择的非易失性存储单元。 通过检测连接到全局位线的读出放大器来检测选择非易失性存储单元的状态，而不是一个全局位线。 在动态编程操作中，第一和第二全局位线及其相关联的局部位线被预充电到第一电压。 第一或第二全局位线之一及其相关的局部位线连接到第二电压。

公开(公告)号：US20090290430A1

公开(公告)日：2009-11-26

申请号：US12126853

申请日：2008-05-23

申请人： Jack Frayer ,  Ya-Fen Lin ,  Gianfranco Pellegrini ,  William Saiki ,  Changyuan Chen ,  Xiuhong Chen

发明人： Jack Frayer ,  Ya-Fen Lin ,  Gianfranco Pellegrini ,  William Saiki ,  Changyuan Chen ,  Xiuhong Chen

IPC分类号： G11C16/06

CPC分类号： G11C16/0475 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0458 ,  G11C16/0491 ,  G11C2211/5612

摘要： A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. The array of non-volatile memory cells are arranged in a plurality of rows and columns, wherein each cell in the same column share a first local bit line to one side and share a second local bit line to another side. Alternating local bit lines are connected to a first global bit line and other alternating local bit lines are connected to a second global bit line with the global bit lines connected to a sense amplifier. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged voltage. One of the first or second global bit lines is connected to a low voltage such as ground, wherein the one global bit line connected to ground also connects to the local bit line for sensing the select non-volatile memory cell. The state of the select non-volatile memory cell is detected by detecting the sense amplifier connected to the global bit line, other than the one global bit line. In a dynamic programming operation, the first and second global bit lines and their associated local bit lines are precharged to a first voltage. One of the first or second global bit line and its associated local bit lines is connected to a second voltage, wherein the associated local bit lines of the one global bit line include a select bit line connected to a programming terminal of the select non-volatile memory cell. The voltage differential between the second voltage and the first voltage is insufficient to cause programming of the select non-volatile memory cell. The bit line, other than the select bit line of the select non-volatile memory cell, is connected to a low voltage such as ground. The voltage differential between the second voltage and ground is sufficient to cause programming of the select non-volatile memory cell. In another embodiment of the programming operation, a local bit line connected to a programming terminal of a select non-volatile memory cell is precharged to a first voltage and then boosted to a programming voltage by precharging an adjacent local bit line.

公开(公告)号：US20060072363A1

公开(公告)日：2006-04-06

申请号：US11283195

申请日：2005-11-18

申请人： Hieu Tran ,  Jack Frayer ,  William Saiki ,  Michael Briner

发明人： Hieu Tran ,  Jack Frayer ,  William Saiki ,  Michael Briner

IPC分类号： G11C7/02

CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C16/28

摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.

公开(公告)号：US20060017084A1

公开(公告)日：2006-01-26

申请号：US10897045

申请日：2004-07-22

申请人： Feng Gao ,  Changyuan Chen ,  Vishal Sarin ,  William Saiki ,  Hieu Tran ,  Dana Lee

发明人： Feng Gao ,  Changyuan Chen ,  Vishal Sarin ,  William Saiki ,  Hieu Tran ,  Dana Lee

IPC分类号： H01L29/76

CPC分类号： H01L27/0805 ,  H01L27/0811 ,  H01L29/94

摘要： An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results.

摘要翻译： 集成的MIS电容器具有两个基本相同的MIS电容器。 第一电容器包括在半导体衬底中与第一导电类型的沟道区相邻的第一导电类型的第一区域。 半导体衬底具有第二导电类型。 栅电极与第一电容器的沟道区隔离并隔开。 第二电容器基本上与第一电容器相同，并且形成在相同的半导体衬底中。 第一电容器的栅电极电连接到第二电容器的第一区域，并且第二电容器的栅极电连接到第一电容器的第一区域。 以这种方式，电容器以反并联配置连接。 具有高电容密度，低工艺复杂性，双极性操作，低电压和温度系数，低外部寄生电阻和电容以及用于可与现有半导体工艺结合的模拟设计的良好匹配特性的电容器。

公开(公告)号：US20100039864A1

公开(公告)日：2010-02-18

申请号：US12190409

申请日：2008-08-12

申请人： Vishal Sarin ,  Dzung Nguyen ,  Jonathan Pabustan ,  Jung Sheng Hoei ,  Jason Guo ,  William Saiki

发明人： Vishal Sarin ,  Dzung Nguyen ,  Jonathan Pabustan ,  Jung Sheng Hoei ,  Jason Guo ,  William Saiki

IPC分类号： G11C16/16 ,  G11C8/00

CPC分类号： G11C16/344 ,  G11C16/0483 ,  G11C16/3445

摘要： Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.

摘要翻译： 公开了诸如涉及包括存储器块的闪速存储器件的方法和装置。 存储块包括基本上彼此平行延伸的多条数据线，以及多个存储单元。 一种这样的方法包括擦除存储器单元; 并对存储器单元执行擦除验证。 擦除验证包括由一个存储器单元确定耦合到数据线之一中的各个存储器单元是否已经被擦除的一个存储器单元。 该方法还可以包括执行至少部分地基于擦除验证的结果来选择性地重新擦除未故障存储器单元的重擦除操作。

公开(公告)号：US20050088221A1

公开(公告)日：2005-04-28

申请号：US10991301

申请日：2004-11-16

申请人： William Saiki ,  Hieu Tran ,  Sakhawat Khan

发明人： William Saiki ,  Hieu Tran ,  Sakhawat Khan

IPC分类号： G11C16/30 ,  H02M3/07 ,  G05F3/02

CPC分类号： H02M3/07 ,  G11C16/30

摘要： A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.

公开(公告)号：US20100046300A1

公开(公告)日：2010-02-25

申请号：US12195552

申请日：2008-08-21

申请人： Vishal Sarin ,  William Saiki ,  Frankie F. Roohparvar

发明人： Vishal Sarin ,  William Saiki ,  Frankie F. Roohparvar

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621

摘要： Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed.

摘要翻译： 公开了减少快速充电损失效应的方法，编程方法，存储器件和存储器系统。 在一种这样的方法中，将编程脉冲施加到字线以增加正被编程的存储器单元的阈值电压。 在编程脉冲之后，将负电压脉冲施加到字线，以将捕获在存储器单元的隧道氧化物中的任何电子强制编程回隧道区域。 在负脉冲之后，执行程序验证操作。

公开(公告)号：US07835190B2

公开(公告)日：2010-11-16

申请号：US12190409

申请日：2008-08-12

申请人： Vishal Sarin ,  Dzung Nguyen ,  Jonathan Pabustan ,  Jung Sheng Hoei ,  Jason Guo ,  William Saiki

发明人： Vishal Sarin ,  Dzung Nguyen ,  Jonathan Pabustan ,  Jung Sheng Hoei ,  Jason Guo ,  William Saiki

IPC分类号： G11C11/34

CPC分类号： G11C16/344 ,  G11C16/0483 ,  G11C16/3445

摘要： Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.

摘要翻译： 公开了诸如涉及包括存储器块的闪速存储器件的方法和装置。 存储块包括基本上彼此平行延伸的多条数据线，以及多个存储单元。 一种这样的方法包括擦除存储器单元; 并对存储器单元执行擦除验证。 擦除验证包括由一个存储器单元确定耦合到数据线之一中的各个存储器单元是否已经被擦除的一个存储器单元。 该方法还可以包括执行至少部分地基于擦除验证的结果来选择性地重新擦除未故障存储器单元的重擦除操作。

公开(公告)号：US08169832B2

公开(公告)日：2012-05-01

申请号：US12909414

申请日：2010-10-21

申请人： Vishal Sarin ,  Dzung Nguyen ,  Jonathan Pabustan ,  Jung Sheng Hoei ,  Jason Guo ,  William Saiki

发明人： Vishal Sarin ,  Dzung Nguyen ,  Jonathan Pabustan ,  Jung Sheng Hoei ,  Jason Guo ,  William Saiki

IPC分类号： G11C11/34

CPC分类号： G11C16/344 ,  G11C16/0483 ,  G11C16/3445

摘要： Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.

摘要翻译： 公开了诸如涉及包括存储器块的闪速存储器件的方法和装置。 存储块包括基本上彼此平行延伸的多条数据线，以及多个存储单元。 一种这样的方法包括擦除存储器单元; 并对存储器单元执行擦除验证。 擦除验证包括由一个存储器单元确定耦合到数据线之一中的各个存储器单元是否已经被擦除的一个存储器单元。 该方法还可以包括执行至少部分地基于擦除验证的结果来选择性地重新擦除未故障存储器单元的重擦除操作。

公开(公告)号：US20120008409A1

公开(公告)日：2012-01-12

申请号：US13236765

申请日：2011-09-20

申请人： Vishal SARIN ,  William Saiki ,  Frankie F. Roohparvar

发明人： Vishal SARIN ,  William Saiki ,  Frankie F. Roohparvar

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621

摘要： Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed.

摘要翻译： 公开了减少快速充电损失效应的方法，编程方法，存储器件和存储器系统。 在一种这样的方法中，将编程脉冲施加到字线以增加正被编程的存储器单元的阈值电压。 在编程脉冲之后，将负电压脉冲施加到字线，以将捕获在存储器单元的隧道氧化物中的任何电子强制编程回隧道区域。 在负脉冲之后，执行程序验证操作。