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    Memory cell comprising an OTP nonvolatile memory unit and a SRAM unit
    3.
    发明申请
    Memory cell comprising an OTP nonvolatile memory unit and a SRAM unit 有权
    存储单元包括OTP非易失性存储单元和SRAM单元

    公开(公告)号：US20070133334A1

    公开(公告)日：2007-06-14

    申请号：US11356805

    申请日：2006-02-17

    申请人： Jack Peng ,  David Fong ,  Harry Luan ,  Jianguo Wang ,  Zhongshang Liu

    发明人： Jack Peng ,  David Fong ,  Harry Luan ,  Jianguo Wang ,  Zhongshang Liu

    IPC分类号： G11C17/18

    CPC分类号： G11C17/16 ,  G11C2216/26

    摘要： Memory cells comprising an SRAM and an OTP memory unit are disclosed that combine the advantages of both technologies and can be fabricated by standard CMOS manufacturing without additional masking. Disclosed concepts and details may be applied to and utilized in other systems requiring memory and/or employing other fabrication technologies. Among other advantages, the SRAM part of disclosed memory cells allows countless programming of the cell, which is useful, for example, during the prototyping. The OTP part is utilized to permanently program the memory cell by either using external data or the data already existing in the SRAM part of the cell. The value held by the OTP unit may also be written directly into the SRAM part of the cell.

    摘要翻译： 公开了包括SRAM和OTP存储器单元的存储器单元，其结合了这两种技术的优点，并且可以通过标准CMOS制造来制造而不需要额外的掩蔽。 公开的概念和细节可以应用于需要存储器和/或采用其它制造技术的其他系统中并被应用。 除了其他优点之外，所公开的存储单元的SRAM部分允许对单元进行无数次编程，这在例如原型设计期间是有用的。 OTP部分用于通过使用外部数据或已经存在于单元的SRAM部分中的数据来永久地编程存储器单元。 OTP单元保存的值也可以直接写入单元的SRAM部分。

    Memory cell comprising an OTP nonvolatile memory unit and a SRAM unit
    4.
    发明授权
    Memory cell comprising an OTP nonvolatile memory unit and a SRAM unit 有权
    存储单元包括OTP非易失性存储单元和SRAM单元

    公开(公告)号：US07277348B2

    公开(公告)日：2007-10-02

    申请号：US11356805

    申请日：2006-02-17

    申请人： Jack Zezhong Peng ,  David Fong ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshang Liu

    发明人： Jack Zezhong Peng ,  David Fong ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshang Liu

    IPC分类号： G11C17/18

    CPC分类号： G11C17/16 ,  G11C2216/26

    摘要： Memory cells including an SRAM and an OTP memory unit that combine the advantages of both technologies and can be fabricated by standard CMOS manufacturing without additional masking. The concepts and details may be applied to and utilized in other systems requiring memory and/or employing other fabrication technologies. Among other advantages, the SRAM part of memory cells allows countless programming of the cell, which is useful, for example, during the prototyping. The OTP part is utilized to permanently program the memory cell by either using external data or the data already existing in the SRAM part of the cell. The value held by the OTP unit may also be written directly into the SRAM part of the cell.

    摘要翻译： 存储单元包括SRAM和OTP存储器单元，其结合了两种技术的优点，并且可以通过标准CMOS制造制造而不需要额外的掩蔽。 概念和细节可以应用于需要存储器和/或采用其它制造技术的其他系统中并被应用。 除了其他优点之外，存储器单元的SRAM部分允许对单元进行无数次的编程，这在原型设计中是有用的。 OTP部分用于通过使用外部数据或已经存在于单元的SRAM部分中的数据来永久地编程存储器单元。 OTP单元保存的值也可以直接写入单元的SRAM部分。

    Non-volatile semiconductor memory based on enhanced gate oxide breakdown
    5.
    发明授权
    Non-volatile semiconductor memory based on enhanced gate oxide breakdown 有权
    基于增强栅极氧化物分解的非易失性半导体存储器

    公开(公告)号：US07471540B2

    公开(公告)日：2008-12-30

    申请号：US11657982

    申请日：2007-01-24

    申请人： Harry Shengwen Luan ,  Zhongshang Liu

    发明人： Harry Shengwen Luan ,  Zhongshang Liu

    IPC分类号： G11C17/08 ,  G11C17/00

    CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203

    摘要： A semiconductor memory structure based on gate oxide break down is constructed in a deep N-well. Thus, the electrical field over the programmable element during the transient procedure of gate oxide break down can be controlled to achieve the best memory programming results. The conductivity of the programmed memory cell is increased greatly and conductivity variation between the memory cells is reduced. This is achieved by adding a body bias during the programming process. The body here refers to a P-well formed within the deep N-Well. Furthermore, the read voltage offset is reduced greatly with this new memory configuration. These improved programming results will allow faster read speed and lower read voltage. This new structure also reduces current leakage from a memory array during programming.

    摘要翻译： 基于栅极氧化物分解的半导体存储器结构构造在深N阱中。 因此，可以控制在栅极氧化物分解的过渡期间在可编程元件上的电场以实现最佳的存储器编程结果。 编程存储单元的电导率大大增加，并且存储单元之间的电导率变化减小。 这是通过在编程过程中增加体偏置来实现的。 这里的身体是指在深N井内形成的P井。 此外，使用这种新的存储器配置，读取电压偏移大大降低。 这些改进的编程结果将允许更快的读取速度和更低的读取电压。 这种新结构还减少了编程期间存储器阵列的电流泄漏。

    3.5 transistor non-volatile memory cell using gate breakdown phenomena
    6.
    发明授权
    3.5 transistor non-volatile memory cell using gate breakdown phenomena 有权
    3.5晶体管非易失性存储单元采用栅极击穿现象

    公开(公告)号：US07173851B1

    公开(公告)日：2007-02-06

    申请号：US11252461

    申请日：2005-10-18

    申请人： John M. Callahan ,  Hemanshu T. Vernenker ,  Michael D. Fliesler ,  Glen Arnold Rosendale ,  Harry Shengwen Luan ,  Zhongshang Liu

    发明人： John M. Callahan ,  Hemanshu T. Vernenker ,  Michael D. Fliesler ,  Glen Arnold Rosendale ,  Harry Shengwen Luan ,  Zhongshang Liu

    IPC分类号： G11C11/34

    CPC分类号： G11C17/18 ,  G11C17/16

    摘要： A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline and a write transistor connected in series at a sense node to said breakdown transistor. The gate of the write transistor is connected to a write wordline. Further, a first sense transistor has its gate connected to the sense node. A second sense transistor is connected in series to the first sense transistor and has its gate connected to a read wordline. The second sense transistor has its source connected to a column bitline.

    摘要翻译： 形成在具有列位线和行字线的存储器阵列中有用的可编程存储器单元。 存储单元包括其栅极连接到程序字线的击穿晶体管和在感测节点处串联连接到所述击穿晶体管的写入晶体管。 写晶体管的栅极连接到写字线。 此外，第一感测晶体管的栅极连接到感测节点。 第二感测晶体管与第一感测晶体管串联连接，并且其栅极连接到读字线。 第二感测晶体管的源极连接到列位线。