公开(公告)号：US06541866B1

公开(公告)日：2003-04-01

申请号：US09778113

申请日：2001-02-07

申请人： Jacques J. Bertrand ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  George J. Kluth

发明人： Jacques J. Bertrand ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  George J. Kluth

IPC分类号： H01L2348

CPC分类号： H01L21/28052 ,  H01L29/4941

摘要： Nickel silicidation of a gate electrode is controlled using a cobalt barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of cobalt thereon and an upper polycrystalline silicon layer on the cobalt layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel suicide and a cobalt silicide barrier layer is formed preventing nickel from reacting with the lower polycrystalline silicon layer.

摘要翻译： 使用钴阻挡层控制栅电极的镍硅化。 实施例包括形成包括下多晶硅层，钴层上的钴层和钴层上的上多晶硅层的栅电极结构，沉积镍层和硅化物，由此将上多晶硅层转化为硅化镍， 形成防止镍与下部多晶硅层反应的硅化钴阻挡层。

公开(公告)号：US06562718B1

公开(公告)日：2003-05-13

申请号：US09729700

申请日：2000-12-06

申请人： Qi Xiang ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  George J. Kluth ,  Minh V. Ngo ,  Eric N. Paton ,  Christy Mei-Chu Woo

发明人： Qi Xiang ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  George J. Kluth ,  Minh V. Ngo ,  Eric N. Paton ,  Christy Mei-Chu Woo

IPC分类号： H01L2144

CPC分类号： H01L29/66507 ,  H01L21/28097

摘要： A method of forming a fully silicidized gate of a semiconductor device includes forming silicide in active regions and a portion of a gate. A shield layer is blanket deposited over the device. The top surface of the gate electrode is then exposed. A refractory metal layer is deposited and annealing is performed to cause the metal to react with the gate and fully silicidize the gate, with the shield layer protecting the active regions of the device from further silicidization to thereby prevent spiking and current leakage in the active regions.

摘要翻译： 形成半导体器件的完全硅化栅极的方法包括在有源区和门的一部分中形成硅化物。 屏蔽层被覆盖在该器件上。 然后露出栅电极的顶表面。 沉积难熔金属层并进行退火以使金属与栅极反应并使栅极完全硅化，屏蔽层保护器件的有源区不受另外的硅化，从而防止有源区中的峰值和电流泄漏 。

公开(公告)号：US06555453B1

公开(公告)日：2003-04-29

申请号：US10058219

申请日：2002-01-29

申请人： Qi Xiang ,  Christy Mei-Chu Woo ,  George J. Kluth

发明人： Qi Xiang ,  Christy Mei-Chu Woo ,  George J. Kluth

IPC分类号： H01L2128

CPC分类号： H01L29/66507 ,  H01L21/2257 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/4975 ,  H01L29/6659

摘要： Semiconductor devices having fully metal silicided gate electrodes, and methods for making the same, are disclosed. The devices have shallow S/D extensions with depths of less than about 500 Å. The methods for making the subject semiconductor devices employ diffusion of dopant from metal suicides to form shallow S/D extensions, followed by high energy implantation and activation, and metal silicidation to form S/D junctions having metal silicide connect regions and a fully metal silicided electrode.

摘要翻译： 公开了具有完全金属硅化物栅电极的半导体器件及其制造方法。 这些器件具有深度小于约500的浅的S / D延伸。 制造本发明的半导体器件的方法是使用掺杂剂从金属硅化物扩散以形成浅的S / D扩展，接着是高能量注入和激活，以及金属硅化以形成具有金属硅化物连接区域和全金属硅化物的S / D结 电极。

公开(公告)号：US06602754B1

公开(公告)日：2003-08-05

申请号：US10059039

申请日：2002-01-30

申请人： George J. Kluth ,  Minh Van Ngo ,  Paul R. Besser

发明人： George J. Kluth ,  Minh Van Ngo ,  Paul R. Besser

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/265

摘要： Bridging between silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by implanting the exposed surfaces of the silicon nitride sidewall spacers with nitrogen to create a surface region having an increased nitrogen concentration. Embodiments include implanting the silicon nitride sidewall spacers with nitrogen such that the nitrogen concentration of the exposed surface is increased by about 5% to about 15%, thereby substantially preventing the formation of metal silicide on the sidewall spacers.

摘要翻译： 通过用氮气注入氮化硅侧壁间隔物的暴露表面以产生具有增加的氮浓度的表面区域来防止在栅电极上的硅化物层与沿着氮化硅侧壁间隔物的源/漏区之间的桥接。 实施例包括用氮气注入氮化硅侧壁间隔物，使得暴露表面的氮浓度增加约5％至约15％，从而基本上防止在侧壁间隔物上形成金属硅化物。

公开(公告)号：US06627504B1

公开(公告)日：2003-09-30

申请号：US09778114

申请日：2001-02-07

申请人： Jacques J. Bertrand ,  George J. Kluth

发明人： Jacques J. Bertrand ,  George J. Kluth

IPC分类号： H01L21336

CPC分类号： H01L29/66553 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by recessing the silicon nitride spacers and forming barrier spacers on top of the silicon nitride spacers. The barrier spacers prevent silicon migration and hence the formation of bridging silicide on the silicon nitride sidewall spacers.

摘要翻译： 通过在氮化硅间隔物的顶部凹入氮化硅间隔物并形成阻挡隔离物来防止在栅电极上的硅化镍层与沿着氮化硅侧壁间隔物的源极/漏极区之间的桥接。 阻挡间隔物防止硅迁移，从而在氮化硅侧壁间隔物上形成桥接硅化物。

公开(公告)号：US06841449B1

公开(公告)日：2005-01-11

申请号：US10061345

申请日：2002-02-04

申请人： Jacques J. Bertrand ,  George J. Kluth

发明人： Jacques J. Bertrand ,  George J. Kluth

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/44

CPC分类号： H01L29/665 ,  H01L21/28518

摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are formed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with oxygen gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.

摘要翻译： 亚微米尺寸的超浅结MOS和/或CMOS晶体管器件通过自对准硅化物工艺形成，其中覆盖镍层形成为与邻近侧壁间隔物的衬底表面的暴露部分接触，栅极的顶表面 电极和侧壁间隔物。 实施例包括通过以下顺序的步骤形成镍覆盖层：（i）通过用氧气溅射形成镍层; 和（ii）用氩气溅射形成镍层。 用于形成镍覆盖层的两步工艺有利于防止在绝缘侧壁间隔物的外表面上形成硅化镍。

公开(公告)号：US06632740B1

公开(公告)日：2003-10-14

申请号：US10061350

申请日：2002-02-04

申请人： Jacques J. Bertrand ,  George J. Kluth

发明人： Jacques J. Bertrand ,  George J. Kluth

IPC分类号： H01L214763

CPC分类号： H01L29/665 ,  H01L21/28518

摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are fomxed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with nitrogen gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.

摘要翻译： 亚微米尺寸的超浅结MOS和/或CMOS晶体管器件由自对准硅化物工艺引起，其中覆盖镍层形成为与邻近侧壁间隔物的衬底表面的暴露部分接触，栅极的顶表面 电极和侧壁间隔物。 实施例包括通过以下顺序的步骤形成镍覆盖层：（i）用氮气溅射形成镍层; 和（ii）用氩气溅射形成镍层。 用于形成镍覆盖层的两步工艺有利于防止在绝缘侧壁间隔物的外表面上形成硅化镍。

公开(公告)号：US08716828B2

公开(公告)日：2014-05-06

申请号：US13473175

申请日：2012-05-16

申请人： Richard J. Carter ,  George J. Kluth ,  Michael J. Hargrove

发明人： Richard J. Carter ,  George J. Kluth ,  Michael J. Hargrove

IPC分类号： H01L21/70

CPC分类号： H01L21/76232

摘要： A semiconductor device includes a layer of semiconductor material having an active transistor region defined therein, an isolation trench formed in the semiconductor material adjacent the active transistor region, and a trench liner lining the isolation trench, wherein the trench liner is formed from a material that substantially inhibits formation of high-k material thereon, and wherein the isolation trench and the trench liner together form a lined trench. The device has an insulating material in the lined trench, and high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, such that the trench liner divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region.

摘要翻译： 半导体器件包括其中限定有活性晶体管区域的半导体材料层，形成在与有源晶体管区域相邻的半导体材料中的隔离沟槽和衬在隔离沟槽上的沟槽衬垫，其中沟槽衬垫由材料形成， 基本上禁止在其上形成高k材料，并且其中隔离沟槽和沟槽衬里一起形成衬里的沟槽。 该器件在衬里沟槽中具有绝缘材料，并且高k栅极材料覆盖绝缘材料的至少一部分并且覆盖有源晶体管区域的至少一部分，使得沟槽衬垫将高k 栅极材料覆盖绝缘材料的至少一部分与覆盖有源晶体管区域的至少一部分的高k栅极材料。

公开(公告)号：US06872613B1

公开(公告)日：2005-03-29

申请号：US10654689

申请日：2003-09-04

申请人： Qi Xiang ,  Huicai Zhong ,  Jung-Suk Goo ,  Allison K. Holbrook ,  Joong S. Jeon ,  George J. Kluth

发明人： Qi Xiang ,  Huicai Zhong ,  Jung-Suk Goo ,  Allison K. Holbrook ,  Joong S. Jeon ,  George J. Kluth

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L21/823857 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositing the first metal layer over dielectric layer. The method further comprises depositing the second metal layer over the first metal layer. The method further comprises implanting nitrogen in the NMOS region of substrate and converting a first portion of the first metal layer into a metal oxide layer and converting a second portion of the first metal layer into metal nitride layer. The method further comprises forming the NMOS gate and the PMOS gate, where the NMOS gate comprises a segment of metal nitride layer and the PMOS gate comprises a segment of the metal oxide layer.

摘要翻译： 根据一个示例性实施例，一种用于在衬底上将第一和第二金属层集成以形成双金属NMOS栅极和PMOS栅极的方法包括在衬底的NMOS区域和PMOS区域上沉积介电层。 该方法还包括在电介质层上沉积第一金属层。 该方法还包括在第一金属层上沉积第二金属层。 该方法还包括在衬底的NMOS区域中注入氮气，并将第一金属层的第一部分转变为金属氧化物层，并将第一金属层的第二部分转换为金属氮化物层。 该方法还包括形成NMOS栅极和PMOS栅极，其中NMOS栅极包括一段金属氮化物层，PMOS栅极包括金属氧化物层的一段。

公开(公告)号：US06689687B1

公开(公告)日：2004-02-10

申请号：US10061348

申请日：2002-02-04

申请人： Jacques J. J. Bertrand ,  George J. Kluth

发明人： Jacques J. J. Bertrand ,  George J. Kluth

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855

摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are formed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with xenon gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.

摘要翻译： 亚微米尺寸的超浅结MOS和/或CMOS晶体管器件通过自对准硅化物工艺形成，其中覆盖镍层形成为与邻近侧壁间隔物的衬底表面的暴露部分接触，栅极的顶表面 电极和侧壁间隔物。 实施例包括通过以下顺序的步骤形成镍覆盖层：（i）通过溅射用氙气形成镍层; 和（ii）用氩气溅射形成镍层。 用于形成镍覆盖层的两步工艺有利于防止在绝缘侧壁间隔物的外表面上形成硅化镍。