公开(公告)号：US08120058B2

公开(公告)日：2012-02-21

申请号：US12607116

申请日：2009-10-28

申请人： Jae-Eun Park ,  Xinlin Wang ,  Xiangdong Chen

发明人： Jae-Eun Park ,  Xinlin Wang ,  Xiangdong Chen

IPC分类号： H01L29/739

CPC分类号： H01L29/7394 ,  H01L29/66325

摘要： A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.

摘要翻译： 一种形成具有不对称源极和漏极的半导体器件的方法。 在一个实施例中，该方法包括在具有第一导电性阱的衬底的第一部分上形成栅极结构。 第二导电性的第二导电性和漏极区的源极区域形成在第一导电性的阱内，在与存在栅极结构的基板的第一部分相邻的基板的一部分中。 在漏极区域内形成第二导电性的掺杂区域，以在半导体器件的漏极侧提供集成的双极晶体管，其中集电极由第一导电性的阱提供，基极由漏极区域 的第二导电性和发射极由存在于漏极区域中的第二导电性的掺杂区域提供。 还提供了通过上述方法形成的半导体器件。

公开(公告)号：US20110095333A1

公开(公告)日：2011-04-28

申请号：US12607116

申请日：2009-10-28

申请人： Jae-Eun Park ,  Xinlin Wang ,  Xiangdong Chen

发明人： Jae-Eun Park ,  Xinlin Wang ,  Xiangdong Chen

IPC分类号： H01L29/739 ,  H01L21/331

CPC分类号： H01L29/7394 ,  H01L29/66325

摘要： A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.

摘要翻译： 一种形成具有不对称源极和漏极的半导体器件的方法。 在一个实施例中，该方法包括在具有第一导电性阱的衬底的第一部分上形成栅极结构。 第二导电性的第二导电性和漏极区的源极区域形成在第一导电性的阱内，在与存在栅极结构的基板的第一部分相邻的基板的一部分中。 在漏极区域内形成第二导电性的掺杂区域，以在半导体器件的漏极侧提供集成的双极晶体管，其中集电极由第一导电性的阱提供，基极由漏极区域 的第二导电性和发射极由存在于漏极区域中的第二导电性的掺杂区域提供。 还提供了通过上述方法形成的半导体器件。

公开(公告)号：US08237197B2

公开(公告)日：2012-08-07

申请号：US12831310

申请日：2010-07-07

申请人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

发明人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

IPC分类号： H01L29/66

CPC分类号： H01L21/823412 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

摘要翻译： 场效应晶体管包括部分SiGe沟道，即包括位于栅极下方的SiGe沟道部分的沟道部分，以及位于漏极区域附近的位于栅电极的边缘下方的Si沟道部分。 SiGe沟道部分可以位于栅极电介质的正下方，或者可以位于位于栅极电介质正下方的Si沟道层下方。 Si沟道部分位于与SiGe沟道部分相同的深度处，并与晶体管的漏极区域接触。 通过在漏极区附近提供Si沟道部分，晶体管的GIDL电流仅在断开状态下保持在与具有硅沟道的晶体管的GIDL电流相同的水平上。

公开(公告)号：US20120190160A1

公开(公告)日：2012-07-26

申请号：US13428061

申请日：2012-03-23

申请人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

发明人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

IPC分类号： H01L21/335

CPC分类号： H01L21/823412 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

公开(公告)号：US20120007145A1

公开(公告)日：2012-01-12

申请号：US12831310

申请日：2010-07-07

申请人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

发明人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

IPC分类号： H01L29/165 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/823412 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

摘要翻译： 场效应晶体管包括部分SiGe沟道，即包括位于栅极下方的SiGe沟道部分的沟道部分，以及位于漏极区域附近的位于栅电极的边缘下方的Si沟道部分。 SiGe沟道部分可以位于栅极电介质的正下方，或者可以位于位于栅极电介质正下方的Si沟道层下方。 Si沟道部分位于与SiGe沟道部分相同的深度处，并与晶体管的漏极区域接触。 通过在漏极区附近提供Si沟道部分，晶体管的GIDL电流仅在断开状态下保持在与具有硅沟道的晶体管的GIDL电流相同的水平上。

公开(公告)号：US20080237737A1

公开(公告)日：2008-10-02

申请号：US11693254

申请日：2007-03-29

申请人： Xiangdong Chen ,  Jun Jung Kim ,  Young Gun Ko ,  Jae-Eun Park ,  Haining S. Yang

发明人： Xiangdong Chen ,  Jun Jung Kim ,  Young Gun Ko ,  Jae-Eun Park ,  Haining S. Yang

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/7843

摘要： A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.

摘要翻译： 提供一种半导体结构，其包括第一有源半导体区域中的第一半导体器件和第二有源半导体区域中的第二半导体器件。 第一电介质衬垫覆盖在第一半导体器件上，并且第二电介质衬垫覆盖在第二半导体器件上，第二电介质衬垫在重叠区域与第一电介质衬垫重叠。 第二电介质衬垫具有第一部分，第一部分具有与第二栅极导体的顶点接触的第一厚度和从第二栅极导体的周边边延伸的第二部分，第二部分具有基本上大于第一厚度的第二厚度。 第一导电通孔接触第一或第二栅极导体和导电通孔中的至少一个延伸穿过第一和第二电介质衬垫在重叠区域。 第二导电通孔可以接触第二半导体器件的源极区域或漏极区域中的至少一个。

公开(公告)号：US08298897B2

公开(公告)日：2012-10-30

申请号：US13428061

申请日：2012-03-23

申请人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

发明人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

公开(公告)号：US07612414B2

公开(公告)日：2009-11-03

申请号：US11693254

申请日：2007-03-29

申请人： Xiangdong Chen ,  Jun Jung Kim ,  Young Gun Ko ,  Jae-Eun Park ,  Haining S. Yang

发明人： Xiangdong Chen ,  Jun Jung Kim ,  Young Gun Ko ,  Jae-Eun Park ,  Haining S. Yang

IPC分类号： H01L21/8238 ,  H01L23/18

CPC分类号： H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/7843

摘要： A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.

摘要翻译： 提供一种半导体结构，其包括第一有源半导体区域中的第一半导体器件和第二有源半导体区域中的第二半导体器件。 第一电介质衬垫覆盖在第一半导体器件上，并且第二电介质衬垫覆盖在第二半导体器件上，第二电介质衬垫在重叠区域与第一电介质衬垫重叠。 第二电介质衬垫具有第一部分，第一部分具有与第二栅极导体的顶点接触的第一厚度和从第二栅极导体的周边边延伸的第二部分，第二部分具有基本上大于第一厚度的第二厚度。 第一导电通孔接触第一或第二栅极导体和导电通孔中的至少一个延伸穿过第一和第二电介质衬垫在重叠区域。 第二导电通孔可以接触第二半导体器件的源极区域或漏极区域中的至少一个。

公开(公告)号：US08626480B2

公开(公告)日：2014-01-07

申请号：US12574440

申请日：2009-10-06

申请人： Paul Chang ,  Jie Deng ,  Terrence B. Hook ,  Sim Y. Loo ,  Anda C. Mocuta ,  Jae-Eun Park ,  Kern Rim ,  Xiaojun Yu

发明人： Paul Chang ,  Jie Deng ,  Terrence B. Hook ,  Sim Y. Loo ,  Anda C. Mocuta ,  Jae-Eun Park ,  Kern Rim ,  Xiaojun Yu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G01R31/2848 ,  G01R31/3008 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5036

摘要： A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.

摘要翻译： 一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。 泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。 泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。 泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。 该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

公开(公告)号：US20110227136A1

公开(公告)日：2011-09-22

申请号：US12728488

申请日：2010-03-22

申请人： Jae-Eun Park ,  Weipeng Li ,  Deleep R. Nair ,  M. Dean Sciacca ,  Voon-Yew Thean ,  Ava Wan ,  Dong-Hun Lee ,  Yong-Meng Lee

发明人： Jae-Eun Park ,  Weipeng Li ,  Deleep R. Nair ,  M. Dean Sciacca ,  Voon-Yew Thean ,  Ava Wan ,  Dong-Hun Lee ,  Yong-Meng Lee

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/76895 ,  H01L29/665 ,  H01L29/6659

摘要： The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.

摘要翻译： 本公开提供了形成电气装置的方法。 该方法可以从衬底上形成栅极结构开始，其中间隔物直接与栅极结构的侧壁接触。 源极区和漏极区形成在衬底中。 在栅极结构上形成金属半导体合金，间隔物的外侧壁和源极区域和漏极区域中的一个。 在金属半导体合金上形成层间电介质层。 通过金属半导体合金上的层间电介质停止形成通孔。 在通孔中的金属半导体合金形成互连。 本公开还包括通过上述方法制造的结构。