公开(公告)号：US08358303B2

公开(公告)日：2013-01-22

申请号：US12361412

申请日：2009-01-28

申请人： Jae-Woong Kim ,  Suk-Han Lee

发明人： Jae-Woong Kim ,  Suk-Han Lee

IPC分类号： G06T17/00 ,  G06T15/00

CPC分类号： G06F17/10

摘要： Disclosed is a method of searing an address in the octree structure having the same resolution. The method of searching address values of the neighboring cells in the octree structure having the same resolution can include performing address encoding of octree cells by giving an inherent address value that is increased according to a depth level of octree to each cell in the octree structure such that address difference values of neighboring cells in the octree structure has a sequential rule; and searching an address value of a neighboring cell that is in contact by a surface with the selected octree cell by using the sequential rule of the address-encoded address difference value of each octree cell. In accordance with an embodiment of the present invention, it is possible to efficiently search address values of neighboring cells that are in contact with an octree cell.

摘要翻译： 公开了一种在具有相同分辨率的八叉树结构中挖掘地址的方法。 搜索具有相同分辨率的八叉树结构中的相邻小区的地址值的方法可以包括通过给出根据八叉树的深度级别增加的固有地址值来执行八叉树小区的地址编码，所述固有地址值在八叉树结构中的每个小区如 八叉树结构中相邻小区的寻址差值具有顺序规则; 以及通过使用每个八叉树单元的地址编码地址差值的顺序规则来搜索与所选择的八叉树单元接触的相邻小区的地址值。 根据本发明的实施例，可以有效地搜索与八叉树单元接触的相邻小区的地址值。

公开(公告)号：US20050084753A1

公开(公告)日：2005-04-21

申请号：US10963618

申请日：2004-10-14

申请人： Jae-Woong Kim

发明人： Jae-Woong Kim

IPC分类号： H01M10/04 ,  H01M2/00 ,  H01M2/02 ,  H01M2/10 ,  H01M2/26 ,  H01M4/00

CPC分类号： H01M2/0277 ,  H01M2/263 ,  H01M10/0431 ,  H01M10/049

摘要： Separated support tapes are attached to an electrode assembly which includes a negative electrode plate, a positive electrode plate, and a separator for performing charge and discharge operations. The separated support tapes are attached to a lower portion of the electrode assembly so as to allow the electrode assembly to be easily inserted into a can, while reducing the possibility of fire in a secondary battery caused by a hard short when the secondary battery is compressed due to external force applied thereto, preventing battery performance from being deteriorated by allowing electrolyte to sufficiently flow into a lower portion of the electrode assembly, and reducing a manufacturing cost of the secondary battery by minimizing the amount of separated support tape to be used.

摘要翻译： 分离的支撑带附接到电极组件，该电极组件包括用于执行充电和放电操作的负极板，正极板和隔板。 分离的支撑带附接到电极组件的下部，以便允许电极组件容易地插入罐中，同时减少当二次电池被压缩时由硬短路引起的二次电池中的火灾的可能性 由于施加的外力，通过允许电解质充分流入电极组件的下部来防止电池性能劣化，并且通过最小化所使用的分离的支撑带的量来降低二次电池的制造成本。

公开(公告)号：US20060223308A1

公开(公告)日：2006-10-05

申请号：US11421672

申请日：2006-06-01

申请人： Young-Sub You ,  Jae-Woong Kim

发明人： Young-Sub You ,  Jae-Woong Kim

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/28194 ,  H01L21/3141 ,  H01L21/67196 ,  H01L21/67207

摘要： An apparatus for manufacturing a semiconductor includes a polyhedral transfer chamber, a first process module for forming a gate dielectric layer by ALD, and a second process module for thermally treating the gate dielectric layer. The first process module is in communication with a first side of the transfer chamber. The second process module in communication with a second side of the transfer chamber. The apparatus further includes at least one load-lock chamber in communication with a third side of the transfer chamber.

摘要翻译： 用于制造半导体的装置包括多面体转移室，用于通过ALD形成栅极电介质层的第一工艺模块和用于热处理栅极电介质层的第二工艺模块。 第一处理模块与传送室的第一侧连通。 第二处理模块与传送室的第二侧连通。 该装置还包括与传送室的第三侧连通的至少一个装载锁定室。

公开(公告)号：US06764955B2

公开(公告)日：2004-07-20

申请号：US10341766

申请日：2003-01-13

申请人： Jeong-Sic Jeon ,  Jae-Woong Kim

发明人： Jeong-Sic Jeon ,  Jae-Woong Kim

IPC分类号： H01L21302

CPC分类号： H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having a contact window and fabrication methods thereof are provided. A lower dielectric layer, conductive patterns and an upper dielectric layer are formed sequentially on a semiconductor substrate. The lower dielectric layer has a higher isotropic etch rate than that of the upper dielectric layer. The upper dielectric layer and the lower dielectric layer are patterned by anisotropic etching to form a trench without exposing the semiconductor substrate. The resultant structure is subject to isotropic etching to expose the substrate and to form a contact window having a wider width in a lower region than in an upper region without damaging the semiconductor substrate.

公开(公告)号：US08105713B2

公开(公告)日：2012-01-31

申请号：US10963618

申请日：2004-10-14

申请人： Jae-Woong Kim

发明人： Jae-Woong Kim

IPC分类号： H01M2/10 ,  H01M4/00 ,  H01M2/02

CPC分类号： H01M2/0277 ,  H01M2/263 ,  H01M10/0431 ,  H01M10/049

摘要： Separated support tapes are attached to an electrode assembly which includes a negative electrode plate, a positive electrode plate, and a separator for performing charge and discharge operations. The separated support tapes are attached to a lower portion of the electrode assembly so as to allow the electrode assembly to be easily inserted into a can, while reducing the possibility of fire in a secondary battery caused by a hard short when the secondary battery is compressed due to external force applied thereto, preventing battery performance from being deteriorated by allowing electrolyte to sufficiently flow into a lower portion of the electrode assembly, and reducing a manufacturing cost of the secondary battery by minimizing the amount of separated support tape to be used.

摘要翻译： 分离的支撑带附接到电极组件，该电极组件包括用于执行充电和放电操作的负极板，正极板和隔板。 分离的支撑带附接到电极组件的下部，以便允许电极组件容易地插入罐中，同时减少当二次电池被压缩时由硬短路引起的二次电池中的火灾的可能性 由于施加的外力，通过允许电解质充分流入电极组件的下部来防止电池性能劣化，并且通过最小化所使用的分离的支撑带的量来降低二次电池的制造成本。

公开(公告)号：US06919640B2

公开(公告)日：2005-07-19

申请号：US10823485

申请日：2004-04-12

申请人： Jeong-Sic Jeon ,  Jae-Woong Kim

发明人： Jeong-Sic Jeon ,  Jae-Woong Kim

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/461 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522

CPC分类号： H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having a contact window and fabrication methods thereof are provided. A lower dielectric layer, conductive patterns and an upper dielectric layer are formed sequentially on a semiconductor substrate. The lower dielectric layer has a higher isotropic etch rate than that of the upper dielectric layer. The upper dielectric layer and the lower dielectric layer are patterned by anisotropic etching to form a trench without exposing the semiconductor substrate. The resultant structure is subject to isotropic etching to expose the substrate and to form a contact window having a wider width in a lower region than in an upper region without damaging the semiconductor substrate.

摘要翻译： 提供具有接触窗的半导体器件及其制造方法。 在半导体基板上依次形成下介电层，导电图案和上电介质层。 下介电层具有比上介电层更高的各向同性蚀刻速率。 通过各向异性蚀刻对上电介质层和下电介质层进行图案化以形成沟槽而不暴露半导体衬底。 所得结构经受各向同性蚀刻以暴露衬底并且形成在下区域中具有比在上部区域中更宽的宽度的接触窗口，而不损坏半导体衬底。

公开(公告)号：US07172971B2

公开(公告)日：2007-02-06

申请号：US11149571

申请日：2005-06-09

申请人： Jeong-Sic Jeon ,  Jae-Woong Kim

发明人： Jeong-Sic Jeon ,  Jae-Woong Kim

IPC分类号： H01L21/302

CPC分类号： H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having a contact window and fabrication methods thereof are provided. A lower dielectric layer, conductive patterns and an upper dielectric layer are formed sequentially on a semiconductor substrate. The lower dielectric layer has a higher isotropic etch rate than that of the upper dielectric layer. The upper dielectric layer and the lower dielectric layer are patterned by anisotropic etching to form a trench without exposing the semiconductor substrate. The resultant structure is subject to isotropic etching to expose the substrate and to form a contact window having a wider width in a lower region than in an upper region without damaging the semiconductor substrate.

摘要翻译： 提供具有接触窗的半导体器件及其制造方法。 在半导体基板上依次形成下介电层，导电图案和上电介质层。 下介电层具有比上介电层更高的各向同性蚀刻速率。 通过各向异性蚀刻对上电介质层和下电介质层进行图案化以形成沟槽而不暴露半导体衬底。 所得结构经受各向同性蚀刻以暴露衬底并且形成在下区域中具有比在上部区域中更宽的宽度的接触窗口，而不损坏半导体衬底。

公开(公告)号：US07077929B2

公开(公告)日：2006-07-18

申请号：US10835372

申请日：2004-04-28

申请人： Young-Sub You ,  Jae-Woong Kim

发明人： Young-Sub You ,  Jae-Woong Kim

IPC分类号： H01L21/306 ,  C23F1/00 ,  C23C16/00

CPC分类号： H01L21/28194 ,  H01L21/3141 ,  H01L21/67196 ,  H01L21/67207

摘要： An apparatus for manufacturing a semiconductor includes a polyhedral transfer chamber, a first process module for forming a gate dielectric layer by ALD, and a second process module for thermally treating the gate dielectric layer. The first process module is in communication with a first side of the transfer chamber. The second process module in communication with a second side of the transfer chamber. The apparatus further includes at least one load-lock chamber in communication with a third side of the transfer chamber.

摘要翻译： 用于制造半导体的装置包括多面体转移室，用于通过ALD形成栅极电介质层的第一工艺模块和用于热处理栅极电介质层的第二工艺模块。 第一处理模块与传送室的第一侧连通。 第二处理模块与传送室的第二侧连通。 该装置还包括与传送室的第三侧连通的至少一个加载锁定室。

公开(公告)号：US20050233584A1

公开(公告)日：2005-10-20

申请号：US11149571

申请日：2005-06-09

申请人： Jeong-Sic Jeon ,  Jae-Woong Kim

发明人： Jeong-Sic Jeon ,  Jae-Woong Kim

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/461 ,  H01L21/768 ,  H01L23/485

CPC分类号： H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having a contact window and fabrication methods thereof are provided. A lower dielectric layer, conductive patterns and an upper dielectric layer are formed sequentially on a semiconductor substrate. The lower dielectric layer has a higher isotropic etch rate than that of the upper dielectric layer. The upper dielectric layer and the lower dielectric layer are patterned by anisotropic etching to form a trench without exposing the semiconductor substrate. The resultant structure is subject to isotropic etching to expose the substrate and to form a contact window having a wider width in a lower region than in an upper region without damaging the semiconductor substrate.

摘要翻译： 提供具有接触窗的半导体器件及其制造方法。 在半导体基板上依次形成下介电层，导电图案和上电介质层。 下介电层具有比上介电层更高的各向同性蚀刻速率。 通过各向异性蚀刻对上电介质层和下电介质层进行图案化以形成沟槽而不暴露半导体衬底。 所得结构经受各向同性蚀刻以暴露衬底并且形成在下区域中具有比在上部区域中更宽的宽度的接触窗口，而不损坏半导体衬底。