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公开(公告)号：US06373343B1
公开(公告)日：2002-04-16
申请号：US09649367
申请日：2000-08-28
IPC分类号： H03B524
CPC分类号： H03K3/0231
摘要： An integrated circuit (10) is disclosed comprising a fundamental frequency oscillator comprising a reference node (32) whose voltage varies between a high threshold and a low threshold. The fundamental frequency oscillator is operable to generate a first output at the fundamental frequency on a first output node (36). The integrated circuit (10) also comprises a circuit (C2) coupled to the reference node. The circuit (C2) is operable to sense the voltage at the reference node (32), to determine when the voltage exceeds an intermediate threshold between the high threshold and the low threshold, and to generate a second output in response to the determination. The integrated circuit (10) also comprises logic (40) coupled to the circuit (C2) and load circuitry (50) coupled to the logic (40). The logic (40) is operable to generate an output signal at an output frequency greater than the fundamental frequency in response to the second output and the first output.
摘要翻译： 公开了一种集成电路（10），其包括基频振荡器，其包括其电压在高阈值和低阈值之间变化的参考节点（32）。 基频振荡器可操作以在第一输出节点（36）上产生基频处的第一输出。 集成电路（10）还包括耦合到参考节点的电路（C2）。 电路（C2）可操作以感测参考节点（32）处的电压，以确定电压何时超过高阈值和低阈值之间的中间阈值，并响应于该确定产生第二输出。 集成电路（10）还包括耦合到电路（C2）的逻辑（40）和耦合到逻辑（40）的负载电路（50）。 逻辑（40）可操作以响应于第二输出和第一输出而以大于基频的输出频率产生输出信号。
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公开(公告)号：US6111737A
公开(公告)日：2000-08-29
申请号：US267490
申请日：1999-03-11
CPC分类号： H01L27/0251
摘要： An internal circuitry protection scheme which protects on-IC circuitry when an external regulator voltage pin is shorted to a higher voltage. The circuit prevents damage to the on-die circuitry that is on the internal voltage rail, by clamping the received voltage, thereby eliminating the chance of damaging the on die circuitry. The circuit offers protection even if the voltage difference is large, but the difference remains small between the internal rail and the external regulated voltage under normal operation.
摘要翻译： 内部电路保护方案，当外部稳压器电压引脚短路到较高电压时，保护IC内部电路。 该电路通过钳位接收到的电压来防止损坏内部电压轨上的片上电路，从而消除了损坏管芯电路的可能性。 即使电压差大，电路也能提供保护，但在正常工作状态下，内部轨道与外部调节电压之间的差异仍然很小。
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公开(公告)号：US06486740B1
公开(公告)日：2002-11-26
申请号：US09651568
申请日：2000-08-28
IPC分类号： H03F114
CPC分类号： H03F1/14
摘要： One aspect of the invention is an integrated circuit (10 or 110) comprising an amplifier (11 or 111) having at least two poles in its frequency response and an output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) coupled to an output node (30) of the amplifier (11 or 111). The output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) is operable to create a feedback signal proportional to the impedance of an output load (50) coupled to the output node (30), and create a zero in the frequency response of the amplifier (11 or 111) in response to the feedback signal between the at least two poles.
摘要翻译： 本发明的一个方面是一种集成电路（10或110），包括在其频率响应中具有至少两个极的放大器（11或111）和输出阻抗补偿电路（M1A，M2，M3，AC1或M1A，M2， M3，M4，AC1）耦合到放大器（11或111）的输出节点（30）。 输出阻抗补偿电路（M1A，M2，M3，AC1或M1A，M2，M3，M4，AC1）可操作以产生与耦合到输出节点（30）的输出负载（50）的阻抗成比例的反馈信号， ，并且响应于至少两个极之间的反馈信号，在放大器（11或111）的频率响应中产生零。
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公开(公告)号：US06169309A
公开(公告)日：2001-01-02
申请号：US09159947
申请日：1998-09-24
IPC分类号： H01L2976
CPC分类号： H01L27/0251
摘要： A circuit for protecting a transistor against electrical transients. The circuit comprises a first diode coupled between a first terminal coupled to a power supply and a control terminal of the protected transistor. The circuit also comprises a second diode and a resistor coupling the control terminal of the protected transistor to a reference potential. A second transistor is coupled in shunt to the protected transistor. The voltage on the control terminal of the second transistor is determined by the current through the resistor. The embodiments may be implemented in an integrated circuit wherein the second, shunting transistor is formed from parasitic elements within the semiconductor body in which the protected transistor is formed. In one embodiment, the protected MOS transistor is formed in an n-well 504 and a shunting bipolar transistor is formed between the n-well 504 and an n-doped guard ring 500 formed adjacent to the n-well in the p-doped substrate 508.
摘要翻译： 用于保护晶体管免受电瞬态的电路。 电路包括耦合在耦合到电源的第一端子和受保护晶体管的控制端子之间的第一二极管。 该电路还包括将受保护晶体管的控制端耦合到参考电位的第二二极管和电阻器。 第二晶体管耦合到分流到保护晶体管。 第二晶体管的控制端子上的电压由通过电阻器的电流决定。 实施例可以在集成电路中实现，其中第二分流晶体管由形成有保护晶体管的半导体主体内的寄生元件形成。 在一个实施例中，被保护的MOS晶体管形成在n阱504中，并且分流双极晶体管形成在n阱504和邻近p掺杂衬底中的n阱附近形成的n掺杂保护环500之间 508。
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5.发明授权
公开(公告)号：US6144070A
公开(公告)日：2000-11-07
申请号：US141496
申请日：1998-08-28
IPC分类号： H01L23/60 , H01L27/02 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/78 , H01L29/76 , H01L23/58 , H01L23/62 , H01L29/94
CPC分类号： H01L29/7816 , H01L23/60 , H01L27/0262 , H01L29/0878 , H01L29/402 , H01L29/7393 , H01L29/7436 , H01L29/7813 , H01L2924/0002
摘要： A transistor including a source region 506 in a semiconductor body 502; a bulk region 508 in the semiconductor body adjacent the source region; a drain region in the semiconductor body adjacent the bulk region but opposite the source region, the drain region including doped regions 504,514 of n and p dopant types; and a field plate 516 formed over the semiconductor body adjacent the drain region between the drain region and the bulk region.
摘要翻译： 一种晶体管，包括半导体本体502中的源极区域506; 邻近源极区域的半导体本体区域508; 所述半导体本体中的漏极区域邻近所述体区域但与所述源极区域相对，所述漏极区域包括n和p掺杂剂类型的掺杂区域504,514; 以及形成在半导体本体上的与漏极区域和主体区域之间的漏极区域相邻的场板516。
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公开(公告)号：US06324044B1
公开(公告)日：2001-11-27
申请号：US09305571
申请日：1999-05-05
IPC分类号： H02H100
CPC分类号： G06F13/385
摘要： A controlled area network (CAN) driver provides improved symmetry between its differential output signals CAN-H and CAN-L, and provides protection for its low voltage devices from voltage transients occurring on its output lines. A plurality of CAN drivers 80 are serially interconnected to form a driver system, wherein each downstream driver stage receives a time-delayed form of the digital input signal TxD, each stage providing a time-delayed contribution to the differential output signals of the overall driver system.
摘要翻译： 控制区域网络（CAN）驱动器在其差分输出信号CAN-H和CAN-L之间提供改进的对称性，并为其低压器件提供对其输出线路上发生的电压瞬变的保护。 多个CAN驱动器80串联互连以形成驱动器系统，其中每个下游驱动器级接收时间延迟形式的数字输入信号TxD，每个级为整个驱动器的差分输出信号提供时间延迟的贡献 系统。
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公开(公告)号：US06407626B1
公开(公告)日：2002-06-18
申请号：US09715759
申请日：2000-11-17
IPC分类号： H03K500
CPC分类号： H03K5/1252 , H03K5/082
摘要： Provided is a symmetrical filter that uses a single comparator. In addition to a voltage divider, a current regulator, and a comparator, the filter of the invention provides control logic that turns on or off a pull up switch and/or pull down switch in order to fully charge or fully discharge a capacitor. Accordingly, in one aspect, the invention is a control logic for a symmetrical filter. Furthermore, timing logic is provided to provide for a more rigorous symmetrical filter performance.
摘要翻译： 提供了使用单个比较器的对称滤波器。 除了分压器，电流调节器和比较器之外，本发明的滤波器还提供控制逻辑，其接通或断开上拉开关和/或下拉开关以便完全充电或完全放电电容器。 因此，一方面，本发明是用于对称滤波器的控制逻辑。 此外，提供定时逻辑以提供更严格的对称滤波器性能。
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公开(公告)号：US06215637B1
公开(公告)日：2001-04-10
申请号：US09290283
申请日：1999-04-13
IPC分类号： H02H322
CPC分类号： H01L27/0259
摘要： A internal circuitry protection scheme which protects on-IC circuitry when an external pin is shorted to a higher than normal voltage. The disclosed solution eliminates cross-talk due to a parasitic NPN.
摘要翻译： 内部电路保护方案，当外部引脚短路到高于正常电压时，保护IC上的电路。 所公开的解决方案消除了由于寄生NPN引起的串扰。
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9.发明授权Reducing the natural current limit in a power MOS device by reducing the gate-source voltage 失效通过降低栅源电压降低功率MOS器件的自然电流限制
公开(公告)号：US5579193A
公开(公告)日：1996-11-26
申请号：US486926
申请日：1995-06-07
IPC分类号： H03K17/082 , H02H7/10
CPC分类号： H03K17/0822
摘要： In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, sensing circuitry 30 to sense a predetermined trigger current, and limitation circuitry 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.
摘要翻译： 根据本发明，用于保护集成电路的功率MOS输出装置与过剩漏极电流的输出限流电路包括功率MOS器件110，检测电路30以感测预定的触发电流，以及限制电路20至 将MOS输出装置110上的栅极 - 源极电压降低到预定的大致固定值。 漏极电流ID响应于栅极 - 源极电压从输出端子102流过功率MOS器件110。 短路状态可允许过量的漏极电流ID流过输出端子102.响应于感测触发电流，栅极 - 源极电压被降低。 降低栅极 - 源极电压会提高MOS器件110的漏极 - 源极电阻并且减少漏极电流ID，使得MOS器件110不会被短路状态损坏。
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公开(公告)号：US06373094B1
公开(公告)日：2002-04-16
申请号：US09908024
申请日：2001-07-18
IPC分类号： H01L29788
摘要： An EEPROM cell (10) formed on a substrate (18) using conventional process steps is provided. The cell (10) includes first (12) and second (14) conductive regions in the substrate (18) below the substrate's outer surface (28), and the first (12) and second (14) conductive regions are laterally displaced from one another by a predetermined distance (32). The cell (10) also includes an insulating layer (20) outwardly from the outer surface (28) of the substrate (18) positioned so that its edges are substantially in alignment between the first (12) and second (14) conductive regions. The cell (10) further includes a floating gate layer (22) outwardly from the insulating layer (20) and in substantially the same shape as the insulating layer (20). The cell (10) also includes a diffusion region (24 or 26) that extends laterally from at least one of the first (12) and second (14) conductive regions so as to overlap with the insulating layer (20). The diffusion region (24 or 26) provides a source of charge for placement on the floating gate layer (22) when programming the EEPROM cell (10).
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