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公开(公告)号：US6111737A
公开(公告)日：2000-08-29
申请号：US267490
申请日：1999-03-11
CPC分类号： H01L27/0251
摘要： An internal circuitry protection scheme which protects on-IC circuitry when an external regulator voltage pin is shorted to a higher voltage. The circuit prevents damage to the on-die circuitry that is on the internal voltage rail, by clamping the received voltage, thereby eliminating the chance of damaging the on die circuitry. The circuit offers protection even if the voltage difference is large, but the difference remains small between the internal rail and the external regulated voltage under normal operation.
摘要翻译： 内部电路保护方案，当外部稳压器电压引脚短路到较高电压时，保护IC内部电路。 该电路通过钳位接收到的电压来防止损坏内部电压轨上的片上电路，从而消除了损坏管芯电路的可能性。 即使电压差大，电路也能提供保护，但在正常工作状态下，内部轨道与外部调节电压之间的差异仍然很小。
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公开(公告)号：US06373343B1
公开(公告)日：2002-04-16
申请号：US09649367
申请日：2000-08-28
IPC分类号： H03B524
CPC分类号： H03K3/0231
摘要： An integrated circuit (10) is disclosed comprising a fundamental frequency oscillator comprising a reference node (32) whose voltage varies between a high threshold and a low threshold. The fundamental frequency oscillator is operable to generate a first output at the fundamental frequency on a first output node (36). The integrated circuit (10) also comprises a circuit (C2) coupled to the reference node. The circuit (C2) is operable to sense the voltage at the reference node (32), to determine when the voltage exceeds an intermediate threshold between the high threshold and the low threshold, and to generate a second output in response to the determination. The integrated circuit (10) also comprises logic (40) coupled to the circuit (C2) and load circuitry (50) coupled to the logic (40). The logic (40) is operable to generate an output signal at an output frequency greater than the fundamental frequency in response to the second output and the first output.
摘要翻译： 公开了一种集成电路（10），其包括基频振荡器，其包括其电压在高阈值和低阈值之间变化的参考节点（32）。 基频振荡器可操作以在第一输出节点（36）上产生基频处的第一输出。 集成电路（10）还包括耦合到参考节点的电路（C2）。 电路（C2）可操作以感测参考节点（32）处的电压，以确定电压何时超过高阈值和低阈值之间的中间阈值，并响应于该确定产生第二输出。 集成电路（10）还包括耦合到电路（C2）的逻辑（40）和耦合到逻辑（40）的负载电路（50）。 逻辑（40）可操作以响应于第二输出和第一输出而以大于基频的输出频率产生输出信号。
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公开(公告)号：US06324044B1
公开(公告)日：2001-11-27
申请号：US09305571
申请日：1999-05-05
IPC分类号： H02H100
CPC分类号： G06F13/385
摘要： A controlled area network (CAN) driver provides improved symmetry between its differential output signals CAN-H and CAN-L, and provides protection for its low voltage devices from voltage transients occurring on its output lines. A plurality of CAN drivers 80 are serially interconnected to form a driver system, wherein each downstream driver stage receives a time-delayed form of the digital input signal TxD, each stage providing a time-delayed contribution to the differential output signals of the overall driver system.
摘要翻译： 控制区域网络（CAN）驱动器在其差分输出信号CAN-H和CAN-L之间提供改进的对称性，并为其低压器件提供对其输出线路上发生的电压瞬变的保护。 多个CAN驱动器80串联互连以形成驱动器系统，其中每个下游驱动器级接收时间延迟形式的数字输入信号TxD，每个级为整个驱动器的差分输出信号提供时间延迟的贡献 系统。
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公开(公告)号：US06486740B1
公开(公告)日：2002-11-26
申请号：US09651568
申请日：2000-08-28
IPC分类号： H03F114
CPC分类号： H03F1/14
摘要： One aspect of the invention is an integrated circuit (10 or 110) comprising an amplifier (11 or 111) having at least two poles in its frequency response and an output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) coupled to an output node (30) of the amplifier (11 or 111). The output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) is operable to create a feedback signal proportional to the impedance of an output load (50) coupled to the output node (30), and create a zero in the frequency response of the amplifier (11 or 111) in response to the feedback signal between the at least two poles.
摘要翻译： 本发明的一个方面是一种集成电路（10或110），包括在其频率响应中具有至少两个极的放大器（11或111）和输出阻抗补偿电路（M1A，M2，M3，AC1或M1A，M2， M3，M4，AC1）耦合到放大器（11或111）的输出节点（30）。 输出阻抗补偿电路（M1A，M2，M3，AC1或M1A，M2，M3，M4，AC1）可操作以产生与耦合到输出节点（30）的输出负载（50）的阻抗成比例的反馈信号， ，并且响应于至少两个极之间的反馈信号，在放大器（11或111）的频率响应中产生零。
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公开(公告)号：US06169309A
公开(公告)日：2001-01-02
申请号：US09159947
申请日：1998-09-24
IPC分类号： H01L2976
CPC分类号： H01L27/0251
摘要： A circuit for protecting a transistor against electrical transients. The circuit comprises a first diode coupled between a first terminal coupled to a power supply and a control terminal of the protected transistor. The circuit also comprises a second diode and a resistor coupling the control terminal of the protected transistor to a reference potential. A second transistor is coupled in shunt to the protected transistor. The voltage on the control terminal of the second transistor is determined by the current through the resistor. The embodiments may be implemented in an integrated circuit wherein the second, shunting transistor is formed from parasitic elements within the semiconductor body in which the protected transistor is formed. In one embodiment, the protected MOS transistor is formed in an n-well 504 and a shunting bipolar transistor is formed between the n-well 504 and an n-doped guard ring 500 formed adjacent to the n-well in the p-doped substrate 508.
摘要翻译： 用于保护晶体管免受电瞬态的电路。 电路包括耦合在耦合到电源的第一端子和受保护晶体管的控制端子之间的第一二极管。 该电路还包括将受保护晶体管的控制端耦合到参考电位的第二二极管和电阻器。 第二晶体管耦合到分流到保护晶体管。 第二晶体管的控制端子上的电压由通过电阻器的电流决定。 实施例可以在集成电路中实现，其中第二分流晶体管由形成有保护晶体管的半导体主体内的寄生元件形成。 在一个实施例中，被保护的MOS晶体管形成在n阱504中，并且分流双极晶体管形成在n阱504和邻近p掺杂衬底中的n阱附近形成的n掺杂保护环500之间 508。
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6.发明授权
公开(公告)号：US6144070A
公开(公告)日：2000-11-07
申请号：US141496
申请日：1998-08-28
IPC分类号： H01L23/60 , H01L27/02 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/78 , H01L29/76 , H01L23/58 , H01L23/62 , H01L29/94
CPC分类号： H01L29/7816 , H01L23/60 , H01L27/0262 , H01L29/0878 , H01L29/402 , H01L29/7393 , H01L29/7436 , H01L29/7813 , H01L2924/0002
摘要： A transistor including a source region 506 in a semiconductor body 502; a bulk region 508 in the semiconductor body adjacent the source region; a drain region in the semiconductor body adjacent the bulk region but opposite the source region, the drain region including doped regions 504,514 of n and p dopant types; and a field plate 516 formed over the semiconductor body adjacent the drain region between the drain region and the bulk region.
摘要翻译： 一种晶体管，包括半导体本体502中的源极区域506; 邻近源极区域的半导体本体区域508; 所述半导体本体中的漏极区域邻近所述体区域但与所述源极区域相对，所述漏极区域包括n和p掺杂剂类型的掺杂区域504,514; 以及形成在半导体本体上的与漏极区域和主体区域之间的漏极区域相邻的场板516。
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公开(公告)号：US06373094B1
公开(公告)日：2002-04-16
申请号：US09908024
申请日：2001-07-18
IPC分类号： H01L29788
摘要： An EEPROM cell (10) formed on a substrate (18) using conventional process steps is provided. The cell (10) includes first (12) and second (14) conductive regions in the substrate (18) below the substrate's outer surface (28), and the first (12) and second (14) conductive regions are laterally displaced from one another by a predetermined distance (32). The cell (10) also includes an insulating layer (20) outwardly from the outer surface (28) of the substrate (18) positioned so that its edges are substantially in alignment between the first (12) and second (14) conductive regions. The cell (10) further includes a floating gate layer (22) outwardly from the insulating layer (20) and in substantially the same shape as the insulating layer (20). The cell (10) also includes a diffusion region (24 or 26) that extends laterally from at least one of the first (12) and second (14) conductive regions so as to overlap with the insulating layer (20). The diffusion region (24 or 26) provides a source of charge for placement on the floating gate layer (22) when programming the EEPROM cell (10).
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公开(公告)号：US5812006A
公开(公告)日：1998-09-22
申请号：US739375
申请日：1996-10-29
申请人： Ross E. Teggatz , Joseph A. Devore , Kenneth G. Buss , Thomas A. Schmidt , Taylor R. Efland , Stephen C. Kwan
发明人： Ross E. Teggatz , Joseph A. Devore , Kenneth G. Buss , Thomas A. Schmidt , Taylor R. Efland , Stephen C. Kwan
IPC分类号： H03K17/06 , H03K17/082 , H03K5/08
CPC分类号： H03K17/063 , H03K17/0822
摘要： An optimized power output clamping structure, includes a power output transistor having a first breakdown voltage and a breakdown structure having a second breakdown voltage coupled to the power output transistor. The second breakdown voltage is less than the first breakdown voltage and follows the first breakdown voltage across all temperature and semiconductor process variations. This feature allows a reduction in breakdown voltage guardbanding and increases output structure reliability. A method of protecting a circuit from inductive flyback is also disclosed. The method includes the steps of driving an inductive load with drive circuitry, turning off the inductive load, and clamping an inductive voltage at a voltage magnitude that protects the drive circuitry from breakdown across all temperature and processing variations.
摘要翻译： 优化的功率输出钳位结构包括具有第一击穿电压的功率输出晶体管和具有耦合到功率输出晶体管的第二击穿电压的击穿结构。 第二击穿电压小于第一击穿电压，并且遵循所有温度和半导体工艺变化的第一击穿电压。 该特征允许降低击穿电压保护带并增加输出结构的可靠性。 还公开了一种保护电路免受感应回扫的方法。 该方法包括以下步骤：利用驱动电路驱动感性负载，关闭感性负载，以及钳位感应电压，电压幅度保护驱动电路不受所有温度和处理变化的影响。
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公开(公告)号：US5675241A
公开(公告)日：1997-10-07
申请号：US672125
申请日：1996-06-27
CPC分类号： G05F3/247
摘要： A circuit and method for providing a low drop out voltage regulator. A source follower circuit is provided having a transistor (MD1) with an output terminal for driving a load at its source terminal and a voltage supply coupled to the drain terminal. At least one diode (D1) is coupled between the gate terminal and a ground reference to provide a predetermined voltage at the gate of the transistor (MD1). A voltage multiplier circuit is provided having an input (IN) for receiving an oscillating input voltage and a charge storage device (39) coupled between the oscillating input and a voltage reference (Vref), and being further coupled in series with the voltage reference and then to the gate terminal of the transistor (MD1). The oscillating input voltage is used to charge the charge storage device (39) to a voltage approximately equal to the voltage reference. When the supply voltage falls below the normal level, the series combination of the voltage reference and the charge storage device provides a multiplied voltage at the gate of the transistor, for example a voltage of twice the reference voltage. This high gate voltage keeps the output at the source of the transistor at a high voltage that is approximately equal to the supply voltage, such that the circuit provides a low drop out voltage under low supply voltage conditions.
摘要翻译： 一种用于提供低压降稳压器的电路和方法。 源极跟随器电路具有晶体管（MD1），其具有用于驱动其源极端子处的负载的输出端子和耦合到漏极端子的电压源。 至少一个二极管（D1）耦合在栅极端子和接地基准之间，以在晶体管（MD1）的栅极处提供预定的电压。 提供了具有用于接收振荡输入电压的输入（IN）和耦合在振荡输入和电压参考（Vref）之间的电荷存储装置（39）的电压倍增器电路，并进一步与电压基准串联耦合， 然后到晶体管（MD1）的栅极端子。 振荡输入电压用于将电荷存储装置（39）充电至大致等于电压基准的电压。 当电源电压低于正常电平时，电压基准和电荷存储装置的串联组合在晶体管的栅极处提供倍增电压，例如两倍于参考电压的电压。 该高栅极电压将晶体管源极处的输出保持在大致等于电源电压的高电压，使得该电路在低电源电压条件下提供低压降电压。
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公开(公告)号：US5710515A
公开(公告)日：1998-01-20
申请号：US480063
申请日：1995-06-07
IPC分类号： G01K7/01 , G01R31/28 , G01R31/30 , G01R31/3167 , H01L23/34 , G01R31/02 , G01R31/00 , G08B21/00
CPC分类号： H01L23/34 , G01K7/01 , G01R31/30 , G01R31/3167 , H01L2924/0002
摘要： A testable temperature warning circuit (120) in an integrated circuit substrate (124) provides a warning if the substrate temperature exceeds a critical temperature. A programming circuit (140) controls a selection, circuit (128) to establish a programmably selectable temperature at either the critical temperature or a second predetermined temperature lower than the critical temperature to enable the warning circuit operation to be tested at a temperature lower than the critical temperature. In one embodiment, the selection circuit 128 comprises a current source that produces a voltage drop across the resistor 121 and base-emitter of the transistor 122 produces a substrate temperature indicating current of magnitude related to the temperature of the substrate. The substrate temperature indicating current at the second temperature is extrapolatingly related to the substrate temperature indicating current at the critical temperature. A method is also presented for testing a temperature warning circuit fabricated in an integrated circuit substrate.
摘要翻译： 如果衬底温度超过临界温度，则集成电路衬底（124）中的可测温度警告电路（120）提供警告。 编程电路（140）控制选择电路（128）在临界温度或低于临界温度的第二预定温度下建立可编程选择的温度，以使报警电路操作能够在低于 临界温度。 在一个实施例中，选择电路128包括在电阻器121上产生电压降的电流源，并且晶体管122的基极 - 发射极产生指示与衬底温度相关的电流幅度的衬底温度。 指示在第二温度下的电流的衬底温度与指示临界温度下的电流的衬底温度外推相关。 还提出了一种用于测试在集成电路基板中制造的温度警告电路的方法。
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