公开(公告)号：US5455200A

公开(公告)日：1995-10-03

申请号：US97505

申请日：1993-07-27

申请人： Charles G. Bigler ,  James J. Casto ,  Michael B. McShane ,  David D. Afshar

发明人： Charles G. Bigler ,  James J. Casto ,  Michael B. McShane ,  David D. Afshar

IPC分类号： H01L21/52 ,  H01L21/60 ,  H01L23/495 ,  H01L23/50 ,  H01L23/544

CPC分类号： H01L23/544 ,  H01L23/4951 ,  H01L23/50 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  Y10S228/904 ,  Y10T29/49121

摘要： A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have central portions (36) which are electrically coupled to peripheral bond pads (14) by conductive wires (30). Inner portions (38) of the leads extend from the central portions toward centerline A--A for improved adhesion and to provide an internal clamping area (41) which stabilizes the leads during wire bonding. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.

摘要翻译： 半导体器件（10）具有片上引线（LOC）配置。 器件的引线（24）具有通过导线（30）电耦合到外围接合焊盘（14）的中心部分（36）。 引线的内部部分（38）从中心部​​分向中心线A-A延伸，以提高粘附力，并提供在引线接合期间稳定引线的内部夹紧区域（41）。 在一个实施例中，引线框架（16）的连接杆（22）用于跨半导体芯片（12）分配功率。 引线框架还可以包括分别将芯片（12）和绝缘带（18）对准引线框的芯片对准特征（50）和带对准特征（52）。

公开(公告)号：US5381036A

公开(公告)日：1995-01-10

申请号：US107412

申请日：1993-08-16

申请人： Charles G. Bigler ,  James J. Casto ,  Michael B. McShane ,  David D. Afshar

发明人： Charles G. Bigler ,  James J. Casto ,  Michael B. McShane ,  David D. Afshar

IPC分类号： H01L21/52 ,  H01L21/60 ,  H01L23/495 ,  H01L23/50 ,  H01L23/544 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC分类号： H01L23/544 ,  H01L23/4951 ,  H01L23/50 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  Y10S228/904 ,  Y10T29/49121

摘要： A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have central portions (36) which are electrically coupled to peripheral bond pads (14) by conductive wires (30). Inner portions (38) of the leads extend from the central portions toward centerline A--A for improved adhesion and to provide an internal clamping area (41) which stabilizes the leads during wire bonding. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.

摘要翻译： 半导体器件（10）具有片上引线（LOC）配置。 器件的引线（24）具有通过导线（30）电耦合到外围接合焊盘（14）的中心部分（36）。 引线的内部部分（38）从中心部​​分向中心线A-A延伸，以提高粘附力，并提供在引线接合期间稳定引线的内部夹紧区域（41）。 在一个实施例中，引线框架（16）的连接杆（22）用于跨半导体芯片（12）分配功率。 引线框架还可以包括分别将芯片（12）和绝缘带（18）对准引线框的芯片对准特征（50）和带对准特征（52）。

公开(公告)号：US5060052A

公开(公告)日：1991-10-22

申请号：US577234

申请日：1990-09-04

申请人： James J. Casto ,  Charles G. Bigler

发明人： James J. Casto ,  Charles G. Bigler

IPC分类号： H01L23/495

CPC分类号： H01L23/49572 ,  H01L2924/0002

摘要： In a TAB bonded semiconductor device, off-chip power and ground distribution is provided by electrically conductive leads spanning across the face of the semiconductor device. Means for supporting at least one TAB lead carrying a power or ground signal across the face of the semiconductor device to an external bonding site is positioned in a central portion of the chip bonding area. In accordance with one embodiment of the invention, a semiconductor device is provided having a plurality of bonding pads arrayed on at least two sides of a face surface thereon. At least one TAB lead is bonded to a bonding pad on a first side of the face surface and spans across the face surface and is bonded to a bonding pad located in a second side of the face surface. An interior tape section overlies a central portion of the face surface supporting the TAB lead.

摘要翻译： 在TAB键合半导体器件中，通过横跨半导体器件的表面的导电引线提供片外电源和接地分布。 用于将携带电源或接地信号的至少一个TAB引线跨过半导体器件的表面支撑到外部接合部位的装置位于芯片接合区域的中心部分。 根据本发明的一个实施例，提供一种半导体器件，其具有排列在其表面的至少两侧上的多个焊盘。 至少一个TAB引线被接合到面表面的第一侧上的接合焊盘，跨越面表面并且结合到位于面表面的第二侧中的接合焊盘。 内部带部分覆盖支撑TAB引线的面表面的中心部分。

公开(公告)号：US5517056A

公开(公告)日：1996-05-14

申请号：US129503

申请日：1993-09-30

申请人： Charles G. Bigler ,  Alan H. Woosley ,  Michael B. McShane

发明人： Charles G. Bigler ,  Alan H. Woosley ,  Michael B. McShane

IPC分类号： H01L23/28 ,  H01L21/56 ,  H01L23/495 ,  H01L23/50 ,  H01L23/02

CPC分类号： H01L21/565 ,  H01L23/49541 ,  H01L2224/49171 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01078

摘要： A leadframe (30) having a novel resin injecting area (44) is disclosed to facilitate and control the removal of a molded gate (18) prior to excising a semiconductor device(70) from a carrier ring (14). The carrier ring has a corner which is on a diagonal with a corner of the package body (12) to form the resin injecting area. The resin injecting area of the leadframe has a hole (48) and an extension bar (50) extending from the hole to connect to a tie bar (36), which supports a die pad (32), inside the package body. The hole in the leadframe is designed for retaining a molded gate. The extension bar is designed to make the removal of a portion of a molded gate easier and more controllable. The semiconductor device can be shipped in the carrier ring with a portion of the molded gate already removed.

摘要翻译： 公开了一种具有新型树脂注入区域（44）的引线框架（30），用于在将半导体器件（70）从载体环（14）切除之前有助于和控制模制浇口（18）的移除。 承载环具有与包装体（12）的角部对角地形成树脂注入区域的角部。 引线框架的树脂注入区域具有从孔延伸的孔（48）和延伸杆（50），以连接到在包装体内部支撑管芯焊盘（32）的连接杆（36）。 引线框中的孔用于保持模制浇口。 延伸杆被设计成使得模制门的一部分的移除更容易和更可控。 半导体器件可以在已经去除模制栅极的一部分的载体环中运输。

公开(公告)号：US4897602A

公开(公告)日：1990-01-30

申请号：US258235

申请日：1988-10-14

申请人： Paul T. Lin ,  Michael B. McShane ,  Charles G. Bigler ,  John A. Goertz ,  Joan M. Hamilton

发明人： Paul T. Lin ,  Michael B. McShane ,  Charles G. Bigler ,  John A. Goertz ,  Joan M. Hamilton

IPC分类号： H01L21/68 ,  H01L21/683

CPC分类号： H01L21/68 ,  H01L21/6835

摘要： An electronic device package on a lead frame with a peripheral carrier structure holding the distal ends of the leads in rigid position. The carrier structure is spaced apart from the package body and permits the package to be handled and tested while protecting the leads. A different, relatively lower quality and less expensive material is used for the carrier structure than for the package body to reduce the cost of the package since the carrier structure may comprise several times, for example four times or more, the volume of the package body.

摘要翻译： 引线框架上的电子器件封装，其具有将引线的远端固定在刚性位置的外围载体结构。 承载结构与包装主体间隔开并允许在保护引线的同时处理和测试包装。 对于载体结构而言，与包装体相比，使用不同的，相对较低的质量和较便宜的材料来降低包装的成本，因为载体结构可以包括包装体的体积的几倍，例如四倍或更多倍 。

公开(公告)号：US5691242A

公开(公告)日：1997-11-25

申请号：US606981

申请日：1996-02-26

申请人： Victor K. Nomi ,  John R. Pastore ,  Charles G. Bigler

发明人： Victor K. Nomi ,  John R. Pastore ,  Charles G. Bigler

IPC分类号： H01L23/04 ,  H01L23/13 ,  H01L23/31 ,  H01L23/544 ,  H01L21/60

CPC分类号： H01L23/544 ,  H01L23/13 ,  H01L23/3121 ,  H01L2223/54473 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181

摘要： A method for packaging an integrated circuit begins by providing an organic substrate (310) having at least one device site (312). Within each device site, one or more electronic devices (532) is mounted. Around the device site, slots (316) and corner holes (318) are formed. In one embodiment, a negative feature, such as a notch (326), is formed in the substrate along the inner edge (315) of the slots. After the electronic device is mounted and encapsulated in a plastic package body (320), the device is excised from the substrate by punching corner regions of a final package perimeter (317). The placement of the slots, corner holes, and notches results in a punch periphery that is free from burrs, provides maximum active interconnect area, and minimizes surface and/or edge damage during the punch operation. Instead of forming notches, a positive feature, such as a protrusion (426) can be incorporated into a punching tool segment (428) to provide the same benefits.

摘要翻译： 一种用于封装集成电路的方法通过提供具有至少一个器件位置（312）的有机衬底（310）开始。 在每个设备站点内安装一个或多个电子设备（532）。 围绕设备现场，形成槽（316）和角孔（318）。 在一个实施例中，沿着槽的内边缘（315）在衬底中形成负特征，例如凹口（326）。 在将电子设备安装并封装在塑料封装主体（320）中之后，通过冲压最终封装周边（317）的拐角区域将装置从基板上排出。 槽，角孔和缺口的放置导致没有毛刺的冲头周边，提供最大的有源互连面积，并且在冲压操作期间最小化表面和/或边缘损伤。 代替形成凹口，可以将诸如突起（426）的积极特征结合到冲压工具段（428）中以提供相同的益处。

公开(公告)号：US4837184A

公开(公告)日：1989-06-06

申请号：US141013

申请日：1988-01-04

申请人： Paul T. Lin ,  Michael B. McShane ,  Charles G. Bigler ,  John A. Goertz

发明人： Paul T. Lin ,  Michael B. McShane ,  Charles G. Bigler ,  John A. Goertz

IPC分类号： H01L23/28 ,  H01L21/68 ,  H01L21/683 ,  H01L23/50

CPC分类号： H01L21/6835 ,  H01L21/68 ,  H01L2224/48091 ,  H01L2224/48247 ,  Y10T29/49004 ,  Y10T29/49121 ,  Y10T29/49172

摘要： An electronic device package on a lead frame with a peripheral carrier structure holding the distal ends of the leads in rigid position. The carrier structure is spaced apart from the package body and permits the package to be handled and tested while protecting the leads. A different, relatively lower quality and less expensive material is used for the carrier structure than for the package body to reduce the cost of the package since the carrier structure may comprise several times, for example four times or more, the volume of the package body.

摘要翻译： 引线框架上的电子器件封装，其具有将引线的远端固定在刚性位置的外围载体结构。 承载结构与包装主体间隔开并允许在保护引线的同时处理和测试包装。 对于载体结构而言，与包装体相比，使用不同的，相对较低的质量和较便宜的材料来降低包装的成本，因为载体结构可以包括包装体的体积的几倍，例如四倍或更多倍 。