公开(公告)号：US5147815A

公开(公告)日：1992-09-15

申请号：US663223

申请日：1991-03-01

申请人： James J. Casto

发明人： James J. Casto

IPC分类号： H01L23/31 ,  H01L23/495

CPC分类号： H01L23/49537 ,  H01L23/315 ,  H01L23/49506 ,  H01L23/49575 ,  H01L2224/05554 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  Y10T29/49121

摘要： A packaged semiconductor device is disclosed having at least two electronic components encapsulated in a single body of standard size and pin-out configuration. In accordance with one embodiment of this invention, two leadframes, having electronic components electrically coupled thereto, are positioned such that the electronic components are in a stacked relationship and the outer portions of the two sets of leads within each leadframe are interdigitated. The configuration enables all components to be accessed independently and minimizes the footprint of the device while maintaining a standard package outline.

摘要翻译： 公开了一种封装的半导体器件，其具有封装在标准尺寸和引脚配置的单体中的至少两个电子部件。 根据本发明的一个实施例，具有电耦合到其上的电子部件的两个引线框架被定位成使得电子部件处于堆叠关系，并且每个引线框架内的两组引线的外部部分交错。 该配置可以独立访问所有组件，并最大限度地减少设备的占用面积，同时保持标准的封装外形。

公开(公告)号：US06732266B1

公开(公告)日：2004-05-04

申请号：US09650630

申请日：2000-08-28

申请人： Charles Anderson ,  James J. Casto ,  Alexander C. Tain

发明人： Charles Anderson ,  James J. Casto ,  Alexander C. Tain

IPC分类号： G06F124

CPC分类号： H05K1/029 ,  H05K2201/10212 ,  H05K2201/10325 ,  H05K2201/10689 ,  H05K2203/176

摘要： An arrangement and method of reconfiguring a circuit board and package arrangement employs one-time programmable elements on a package to allow a programmable first package arrangement having a first package board and a first integrated circuit to be readily replaced. The first package arrangement was programmed to operate with a first set of operating parameters. The replacement package arrangement, having a second package board and a second integrated circuit, may be substantially identical to the first package arrangement except programmed to operate with a second set of operating parameters different from the first set of op crating parameters. The replacement of the first package arrangement by the second, differently programmed package arrangement, provides a reconfigured circuit board and package arrangement while avoiding the obsoleting of the circuit board.

摘要翻译： 重新配置电路板和封装布置的布置和方法在封装上使用一次性可编程元件，以允许具有第一封装板和第一集成电路的可编程第一封装布置容易地被替换。 第一封装装置被编程为用第一组操作参数进行操作。 具有第二封装板和第二集成电路的替换封装装置可以基本上与第一封装布置相同，除了被编程为以与第一组操作参数不同的第二组操作参数进行操作。 通过第二种不同编程的封装布置来替代第一封装布置提供了重新配置的电路板和封装装置，同时避免了电路板的过时。

公开(公告)号：US5045914A

公开(公告)日：1991-09-03

申请号：US663225

申请日：1991-03-01

申请人： James J. Casto ,  Michael B. McShane ,  Paul T. Lin

发明人： James J. Casto ,  Michael B. McShane ,  Paul T. Lin

IPC分类号： H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L25/10 ,  H05K3/34

CPC分类号： H05K3/3436 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49517 ,  H01L23/49589 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K2201/09709 ,  H05K2201/10515 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2201/10924 ,  H05K2201/10931 ,  H05K2201/2036 ,  H05K3/3426 ,  Y02P70/613

摘要： A pad array electronic device for mounting on a substrate, such as a printed circuit board (PCB), has a relatively rigid package body with a plurality of holes bearing connecting mechanisms for bonding to lands on the PCB. The package body may be a thermoset plastic or other material that can be injection molded around an electronic component, such as an integrated circuit (IC) bonded to a lead frame. An integrated circuit die or other electronic component is mounted in proximity with or on the lead frame and electrical connections between the integrated circuit chip and the frame are made by any conventional means. In one aspect, the substrate leads are provided at their outer ends that are exposed by holes in the package with solder balls or pads for making connections to the PCB. The package body may be optionally used to stand off the device a set distance from the PCB so that the solder balls will form the proper concave structure. The periphery of the package body may function as a carrier structure to protect the lead or connection structures during testing, handling and board mounting. The open vias permit back side testing of the device before or after mounting of the package to the PCB. Additionally, a heat sink structure and/or capacitor may be directly bonded to the side or the top of the pad array electronic device which may be used singly or in multiple, stacked configurations, to facilitate the thermal dissipation from the device.

摘要翻译： 用于安装在诸如印刷电路板（PCB）的基板上的焊盘阵列电子器件具有相对刚性的封装体，其具有多个孔，该多个孔承载用于结合到PCB上的焊盘的连接机构。 封装体可以是可以围绕电子部件注射模制的热固性塑料或其它材料，例如结合到引线框架的集成电路（IC）。 集成电路芯片或其他电子部件安装在引线框架附近或之上，并且通过任何常规方式制造集成电路芯片和框架之间的电连接。 在一个方面，衬底引线设置在其外端处，其被封装中的孔暴露以用于与PCB连接的焊球或焊盘。 封装体可以可选地用于从PCB离开设备一定距离，使得焊球将形成适当的凹形结构。 封装主体的周边可以用作载体结构，以在测试，处理和板安装期间保护引线或连接结构。 打开的通孔允许在将封装安装到PCB之前或之后对器件进行背面测试。 此外，散热器结构和/或电容器可以直接结合到可以单独使用或以多个堆叠配置使用的焊盘阵列电子器件的侧面或顶部，以便于从器件散热。

公开(公告)号：US5014113A

公开(公告)日：1991-05-07

申请号：US457444

申请日：1989-12-27

申请人： James J. Casto

发明人： James J. Casto

IPC分类号： H01L21/60 ,  H01L23/495 ,  H01L23/50 ,  H01L23/538 ,  H05K3/34

CPC分类号： H01L23/49534 ,  H05K3/3426 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H05K2201/10689 ,  H05K2201/10909 ,  H05K2201/2081 ,  Y02P70/613

摘要： A lead frame having multiple layers permits fine connection to a large number of bonding pads on an electronic component such as an integrated circuit (IC), but strong external package leads. A fully featured or completely extensive lead frame layer bears proximal ends that may be finely dimensioned for connection with the bonding pads of an IC. A second frame layer is laminated with the first layer, but does not have proximal ends that extend as far as those of the fully featured frame layer. The doubled external leads for mounting to a printed circuit board (PCB) are relatively stronger than the single, more finely featured proximal lead ends that are bonded to the component. The lead frame layers may also differ with respect to their thicknesses, electrical conductivity, strength and solder-wetting characteristics.

摘要翻译： 具有多个层的引线框允许与诸如集成电路（IC）的电子部件上的大量接合焊盘的精细连接，但是强的外部封装引线。 全功能或完全广泛的引线框架层具有近端，其可以被精细尺寸以与IC的接合焊盘连接。 第二框架层与第一层层叠，但是不具有延伸到全功能框架层的近端的近端。 用于安装到印刷电路板（PCB）的双倍的外部引线比结合到组件的单个更精细的近端引线端相对更强。 引线框架层也可以相对于它们的厚度，电导率，强度和焊料润湿特性而不同。

公开(公告)号：US4924291A

公开(公告)日：1990-05-08

申请号：US261439

申请日：1988-10-24

申请人： Israel A. Lesk ,  George W. Hawkins ,  Ronald E. Thomas ,  William L. Hunter ,  James J. Casto ,  Michael B. McShane

发明人： Israel A. Lesk ,  George W. Hawkins ,  Ronald E. Thomas ,  William L. Hunter ,  James J. Casto ,  Michael B. McShane

IPC分类号： H01L23/34 ,  H01L23/16 ,  H01L23/28 ,  H01L23/31 ,  H01L23/433 ,  H01L23/495 ,  H01L23/50

CPC分类号： H01L23/49568 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L2224/32245 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/1815

摘要： A molded semiconductor package having a flagless leadframe wherein a semiconductor die is disposed in or above a die opening of a leadframe. This allows for thin, symmetrical packages and packages having a minimum number of material interfaces to be manufactured because no leadframe flags and minimal die bond material are employed. The present invention further includes guard rings to protect high stress areas of the semiconductor die from damage and heat spreaders to more effectively spread heat dissipated by the semiconductor die.

公开(公告)号：US5455200A

公开(公告)日：1995-10-03

申请号：US97505

申请日：1993-07-27

申请人： Charles G. Bigler ,  James J. Casto ,  Michael B. McShane ,  David D. Afshar

发明人： Charles G. Bigler ,  James J. Casto ,  Michael B. McShane ,  David D. Afshar

IPC分类号： H01L21/52 ,  H01L21/60 ,  H01L23/495 ,  H01L23/50 ,  H01L23/544

CPC分类号： H01L23/544 ,  H01L23/4951 ,  H01L23/50 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  Y10S228/904 ,  Y10T29/49121

摘要： A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have central portions (36) which are electrically coupled to peripheral bond pads (14) by conductive wires (30). Inner portions (38) of the leads extend from the central portions toward centerline A--A for improved adhesion and to provide an internal clamping area (41) which stabilizes the leads during wire bonding. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.

摘要翻译： 半导体器件（10）具有片上引线（LOC）配置。 器件的引线（24）具有通过导线（30）电耦合到外围接合焊盘（14）的中心部分（36）。 引线的内部部分（38）从中心部​​分向中心线A-A延伸，以提高粘附力，并提供在引线接合期间稳定引线的内部夹紧区域（41）。 在一个实施例中，引线框架（16）的连接杆（22）用于跨半导体芯片（12）分配功率。 引线框架还可以包括分别将芯片（12）和绝缘带（18）对准引线框的芯片对准特征（50）和带对准特征（52）。

公开(公告)号：US5381036A

公开(公告)日：1995-01-10

申请号：US107412

申请日：1993-08-16

申请人： Charles G. Bigler ,  James J. Casto ,  Michael B. McShane ,  David D. Afshar

发明人： Charles G. Bigler ,  James J. Casto ,  Michael B. McShane ,  David D. Afshar

IPC分类号： H01L21/52 ,  H01L21/60 ,  H01L23/495 ,  H01L23/50 ,  H01L23/544 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC分类号： H01L23/544 ,  H01L23/4951 ,  H01L23/50 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  Y10S228/904 ,  Y10T29/49121

摘要： A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have central portions (36) which are electrically coupled to peripheral bond pads (14) by conductive wires (30). Inner portions (38) of the leads extend from the central portions toward centerline A--A for improved adhesion and to provide an internal clamping area (41) which stabilizes the leads during wire bonding. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.

摘要翻译： 半导体器件（10）具有片上引线（LOC）配置。 器件的引线（24）具有通过导线（30）电耦合到外围接合焊盘（14）的中心部分（36）。 引线的内部部分（38）从中心部​​分向中心线A-A延伸，以提高粘附力，并提供在引线接合期间稳定引线的内部夹紧区域（41）。 在一个实施例中，引线框架（16）的连接杆（22）用于跨半导体芯片（12）分配功率。 引线框架还可以包括分别将芯片（12）和绝缘带（18）对准引线框的芯片对准特征（50）和带对准特征（52）。

公开(公告)号：US5060052A

公开(公告)日：1991-10-22

申请号：US577234

申请日：1990-09-04

申请人： James J. Casto ,  Charles G. Bigler

发明人： James J. Casto ,  Charles G. Bigler

IPC分类号： H01L23/495

CPC分类号： H01L23/49572 ,  H01L2924/0002

摘要： In a TAB bonded semiconductor device, off-chip power and ground distribution is provided by electrically conductive leads spanning across the face of the semiconductor device. Means for supporting at least one TAB lead carrying a power or ground signal across the face of the semiconductor device to an external bonding site is positioned in a central portion of the chip bonding area. In accordance with one embodiment of the invention, a semiconductor device is provided having a plurality of bonding pads arrayed on at least two sides of a face surface thereon. At least one TAB lead is bonded to a bonding pad on a first side of the face surface and spans across the face surface and is bonded to a bonding pad located in a second side of the face surface. An interior tape section overlies a central portion of the face surface supporting the TAB lead.

摘要翻译： 在TAB键合半导体器件中，通过横跨半导体器件的表面的导电引线提供片外电源和接地分布。 用于将携带电源或接地信号的至少一个TAB引线跨过半导体器件的表面支撑到外部接合部位的装置位于芯片接合区域的中心部分。 根据本发明的一个实施例，提供一种半导体器件，其具有排列在其表面的至少两侧上的多个焊盘。 至少一个TAB引线被接合到面表面的第一侧上的接合焊盘，跨越面表面并且结合到位于面表面的第二侧中的接合焊盘。 内部带部分覆盖支撑TAB引线的面表面的中心部分。

公开(公告)号：US06449170B1

公开(公告)日：2002-09-10

申请号：US09651893

申请日：2000-08-30

申请人： Quang D. Nguyen ,  Charles Anderson ,  James J. Casto ,  Alexander C. Tain

发明人： Quang D. Nguyen ,  Charles Anderson ,  James J. Casto ,  Alexander C. Tain

IPC分类号： H05K706

CPC分类号： H01L23/57 ,  H01L23/5382 ,  H01L2221/68359 ,  H01L2224/16225 ,  H01L2924/00014 ,  Y10S257/922 ,  H01L2224/0401

摘要： An integrated circuit package includes at least one one-time programmable element, such as a fuse, having a first end and a second end separated by a programmable link. The programmable element is positioned on a surface other than the top surface, e.g., a side surface or the bottom surface of the package substrate to render them less conspicuous to unscrupulous suppliers intent on tampering with the package. The information programmed by the fuses may relate to speed or voltage ratings for a microprocessor.

摘要翻译： 集成电路封装包括至少一个一次性可编程元件，例如熔丝，其具有由可编程链路隔开的第一端和第二端。 可编程元件位于除了包装基板的顶表面（例如侧表面或底表面）之外的表面上，以使得它们不利于供应商意图篡改包装件的显着性。 保险丝编程的信息可能涉及微处理器的速度或电压额定值。

公开(公告)号：US5498767A

公开(公告)日：1996-03-12

申请号：US321643

申请日：1994-10-11

申请人： Wyatt A. Huddleston ,  James J. Casto

发明人： Wyatt A. Huddleston ,  James J. Casto

IPC分类号： G06F17/50 ,  H01L23/485 ,  H01L21/28 ,  H01L21/60

CPC分类号： H01L24/85 ,  G06F17/5068 ,  H01L24/06 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06179 ,  H01L2224/48 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/49179 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/14

摘要： A process for positioning bond pads around a semiconductor die periphery on an octant basis, taking into account both manufacturing and design limitations. The process positions bond pad centers such that the spacing (pitch) increases towards the die corners. The pitch increase is iteratively calculated from an approximated wire angle. The process iteratively recalculates an octant's pad positions until optimum values are converged upon for the approximated wire angle of the cornermost bond pad and for the furthest allowable position for the cornermost bond pad. Once these optimum values are achieved, the resulting bond pad coordinates are stored in memory or a storage media in a format readable by a layout tool being used to design the die (or package). The resulting file is imported into the layout tool, which uses the stored information to physically position bond pads around the die periphery in the die layout.

摘要翻译： 考虑到制造和设计的局限性，以八分圆为基础将接合焊盘定位在半导体管芯外围周围的工艺。 该过程定位接合焊盘中心，使得间距（间距）朝向模具拐角增加。 从近似线角度迭代计算间距增加。 该过程迭代地重新计算八分圆的焊盘位置，直到最佳值收敛于最接近焊接焊盘的近似线角度并且用于最顶层焊盘的最远可允许位置。 一旦实现了这些最佳值，则所得到的接合焊盘坐标被存储在存储器或存储介质中，其格式可由用于设计管芯（或封装）的布局工具读取。 生成的文件被导入到布局工具中，该工具使用存储的信息来在管芯布局中物理地定位焊盘周围的焊盘。