公开(公告)号：US20080016325A1

公开(公告)日：2008-01-17

申请号：US11484970

申请日：2006-07-12

申请人： James P. Laudon ,  Adam R. Talcott ,  Sanjay Patel ,  Thirumalai S. Suresh

发明人： James P. Laudon ,  Adam R. Talcott ,  Sanjay Patel ,  Thirumalai S. Suresh

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3012 ,  G06F9/30127 ,  G06F9/30181 ,  G06F9/383 ,  G06F9/3857 ,  G06F9/3863

摘要： In one embodiment, a processor comprises a core configured to execute instructions; a register file comprising a plurality of storage locations; and a window management unit. The window management unit is configured to operate the plurality of storage locations as a plurality of windows, wherein register addresses encoded into the instructions identify storage locations among a subset of the plurality of storage locations that are within a current window. Additionally, the window management unit is configured to allocate a second window in response to a predetermined event. One of the current window and the second window serves as a checkpoint of register state, and the other one of the current window and the second window is updated in response to instructions processed subsequent to the checkpoint. The checkpoint may be restored if the speculative execution results are discarded.

摘要翻译： 在一个实施例中，处理器包括被配置为执行指令的核心; 包括多个存储位置的寄存器文件; 和窗口管理单元。 窗口管理单元被配置为将多个存储位置操作为多个窗口，其中编码到指令中的寄存器地址识别在当前窗口内的多个存储位置的子集之间的存储位置。 另外，窗口管理单元被配置为响应于预定事件来分配第二窗口。 当前窗口和第二窗口中的一个用作寄存器状态的检查点，并且响应于在检查点之后处理的指令来更新当前窗口和第二窗口中的另一个窗口。 如果抛弃推测执行结果，则可以恢复检查点。

公开(公告)号：US08762951B1

公开(公告)日：2014-06-24

申请号：US11689359

申请日：2007-03-21

申请人： Nicolai Kosche ,  James P. Laudon ,  Adam R. Talcott ,  Sanjay Patel ,  Farnad Sajjadian

发明人： Nicolai Kosche ,  James P. Laudon ,  Adam R. Talcott ,  Sanjay Patel ,  Farnad Sajjadian

IPC分类号： G06F9/44

CPC分类号： G06F11/3476 ,  G06F8/443 ,  G06F11/3409 ,  G06F2201/86 ,  G06F2201/865 ,  G06F2201/87 ,  G06F2201/88

摘要： A system and method for profiling runtime system events of a computer system may include associating a data source type with detected system events. The system events may be detected dependent on information included in a reply message received by a processor in response to a data request or other transaction request message. The reply message may include information characterizing a source type of a source of data included in the reply message. The source type information may indicate that the source is remote or local; that it is a shared or a private storage location; that the data is supplied via a cache-to-cache transfer; or that the data is sourced from a coherency domain other than that of the requesting process. Instructions, events, messages, and replies may be sampled, and extended address information corresponding to the samples may be stored in an event set database for performance analysis.

摘要翻译： 用于分析计算机系统的运行时系统事件的系统和方法可以包括将数据源类型与检测到的系统事件相关联。 可以根据由处理器响应于数据请求或其他事务请求消息而接收到的应答消息中包括的信息来检测系统事件。 回复消息可以包括表征包括在回复消息中的数据源的源类型的信息。 源类型信息可以指示源是远程的或本地的; 它是一个共享或私人存储位置; 数据通过缓存到缓存传输提供; 或者数据来自与请求进程的一致性域之外的一致性域。 可以对指令，事件，消息和答复进行采样，并且与样本相对应的扩展地址信息可以存储在用于性能分析的事件集数据库中。

公开(公告)号：US07281096B1

公开(公告)日：2007-10-09

申请号：US11054850

申请日：2005-02-09

申请人： Ramaswamy Sivaramakrishnan ,  Sunil Vemula ,  Sanjay Patel ,  James P. Laudon

发明人： Ramaswamy Sivaramakrishnan ,  Sunil Vemula ,  Sanjay Patel ,  James P. Laudon

IPC分类号： G06F13/14

CPC分类号： G06F12/0802 ,  G06F9/30047 ,  G06F9/383 ,  Y02D10/13

摘要： A hardware implemented method for writing data to a cache is provided. In this hardware implemented method, a Block Initializing Store (BIS) instruction is received to write the data from a processor core to a memory block. The BIS instruction includes the data from the processor core. Thereafter, a dummy read request is sent to a memory controller and known data is received from the memory controller without accessing a main memory. The known data is then written to the cache and, after the known data is written, the data from the processor core is written to the cache. A system and processor for writing data to the cache also are described.

摘要翻译： 提供了一种用于将数据写入高速缓存的硬件实现方法。 在该硬件实现方法中，接收到块初始化存储（BIS）指令以将数据从处理器核心写入存储器块。 BIS指令包括来自处理器核心的数据。 此后，将虚拟读取请求发送到存储器控制器，并且从存储器控制器接收已知的数据，而不访问主存储器。 然后将已知数据写入高速缓存，并且在已知数据被写入之后，来自处理器核心的数据被写入高速缓存。 还描述了用于将数据写入缓存的系统和处理器。

公开(公告)号：US06049476A

公开(公告)日：2000-04-11

申请号：US126944

申请日：1998-07-31

申请人： James P. Laudon ,  Daniel E. Lenoski ,  John Manton ,  Michael E. Anderson

发明人： James P. Laudon ,  Daniel E. Lenoski ,  John Manton ,  Michael E. Anderson

IPC分类号： G11C7/00 ,  G11C5/00 ,  G11C5/02 ,  G11C11/00 ,  G11C11/401

CPC分类号： G11C5/04 ,  G11C5/00

摘要： A high memory capacity dual in-line memory module (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system including a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities.

摘要翻译： 一种用于基于目录的分布式共享存储器多处理器计算机系统的高存储容量双列直插式存储器模块（DIMM），包括用于存储数据的数据存储器和用于存储对应于至少一部分的状态或目录信息的状态存储器 的数据。 DIMM允许独立访问数据和状态信息。 DIMM可以配置成多个存储容量。

公开(公告)号：US5727150A

公开(公告)日：1998-03-10

申请号：US766363

申请日：1996-12-17

申请人： James P. Laudon ,  Daniel E. Lenoski

发明人： James P. Laudon ,  Daniel E. Lenoski

IPC分类号： G06F12/06 ,  G06F12/08 ,  G06F12/12 ,  G06F13/00

CPC分类号： G06F12/122 ,  G06F12/08

摘要： A page migration controller is described. The page migration controller determines whether a memory page addressed by a memory access request should be migrated from a local processing node to a requester processing node. The page migration controller accesses an array to obtain a first count associated with the addressed memory page and the requester processing node, and a second count associated with the addressed memory page and the local processing node. The first count is incremented, and then the second count is subtracted from the incremented first count to obtain a difference between the second count and the incremented first count. A comparator determines whether the difference is greater than a migration threshold value. If the difference is greater than the migration threshold value, then a migration interrupt is issued.

摘要翻译： 描述页面迁移控制器。 页面迁移控制器确定由存储器访问请求寻址的存储器页是否应当从本地处理节点迁移到请求者处理节点。 页面迁移控制器访问阵列以获得与所寻址的存储器页面和请求者处理节点相关联的第一计数，以及与寻址的存储器页面和本地处理节点相关联的第二计数。 第一计数增加，然后从增加的第一计数中减去第二计数，以获得第二计数和递增的第一计数之间的差。 比较器确定差异是否大于迁移阈值。 如果差值大于迁移阈值，则发出迁移中断。

公开(公告)号：US5680576A

公开(公告)日：1997-10-21

申请号：US435460

申请日：1995-05-05

申请人： James P. Laudon

发明人： James P. Laudon

IPC分类号： G06F12/08

CPC分类号： G06F12/0817 ,  G06F12/0813

摘要： A multiprocessor system having a plurality of requestors, a memory and memory directory controller employing directory-based coherence. The system implements a method to detect dropping of clean-exclusive data. Only one intervention message is permitted to target an exclusive object held by a first requestor, wherein the intervention message is caused by a second requestor. The system detects whether the first requestor has an outstanding writeback for the object targeted by the intervention message, as well as whether the first requestor has a clean-exclusive, dirty-exclusive or invalid copy of the object targeted by the intervention message. A clean-exclusive copy of the object has been dropped when no outstanding writeback is detected and the first requestor has the object in the invalid state.

摘要翻译： 具有多个请求者的多处理器系统，采用基于目录的一致性的存储器和存储器目录控制器。 该系统实现了一种检测清除独占数据丢弃的方法。 仅允许一个干预消息来定位由第一请求者持有的排他对象，其中干预消息由第二请求者引起。 系统检测第一请求者是否具有针对干预消息所针对的对象的未完成的回写，以及第一请求者是否具有由干预消息所针对的对象的干净排他，脏排他或无效的副本。 当没有检测到未完成的回写并且第一请求者的对象处于无效状态时，对象的干净排他性副本已经被丢弃。

公开(公告)号：US20080077743A1

公开(公告)日：2008-03-27

申请号：US11524837

申请日：2006-09-21

申请人： James P. Laudon

发明人： James P. Laudon

IPC分类号： G06F13/28

CPC分类号： G06F12/0837 ,  G06F9/505

摘要： Software-based cache coherence protocol. A processing unit may execute a memory request using a processor thread. In response to detecting a cache hit to shared or a cache miss associated with the memory request, a cache may provide both a trap signal and coherence information to the processor thread of the processing unit. After receiving the trap signal and the coherence information, the processor thread may perform a cache coherence operation for the memory request using at least the received coherence information. The processing unit may include a plurality of processor threads and a load balancer. The load balancer may receive coherence requests from one or more remote processing units and distribute the received coherence requests across the plurality of processor threads. The load balance may preferentially distribute the received coherence requests across the plurality of processor threads based on the operation state of the processor threads.

摘要翻译： 基于软件的缓存一致性协议。 处理单元可以使用处理器线程执行存储器请求。 响应于检测到与存储器请求相关联的共享的缓存命中或高速缓存未命中，高速缓存可以向处理单元的处理器线程提供陷阱信号和一致性信息。 在接收到陷阱信号和相干信息之后，处理器线程可以使用至少所接收的相干信息来执行用于存储器请求的高速缓存一致性操作。 处理单元可以包括多个处理器线程和负载平衡器。 负载平衡器可以从一个或多个远程处理单元接收一致性请求，并且在多个处理器线程上分发所接收的一致性请求。 基于处理器线程的操作状态，负载平衡可以优先地在多个处理器线程上分配所接收的一致性请求。

公开(公告)号：US20080005511A1

公开(公告)日：2008-01-03

申请号：US11477733

申请日：2006-06-29

申请人： James P. Laudon

发明人： James P. Laudon

IPC分类号： G06F12/14

CPC分类号： G06F13/1668 ,  Y02D10/14

摘要： A memory controller including a control unit for limiting the number of memory requests that are executed within a predetermined time period to regulate power consumption. The control unit may determine a memory request limit indicating the maximum number of memory requests that are allowed to be executed during the predetermined time period based on at least a carry-over limit and a new request limit. The carry-over limit may indicate the maximum number of carry-over memory requests that are allowed during the predetermined time period. The new request limit may indicate the maximum number of new memory requests that are allowed during the predetermined time period. The control unit may further control the number of memory requests that are executed in each of a sequence of predetermined time periods.

摘要翻译： 一种存储器控制器，包括用于限制在预定时间段内执行的存储器请求数量以调节功率消耗的控制单元。 控制单元可以至少基于结转限制和新的请求限制来确定指示在预定时间段期间被允许执行的最大存储器请求数量的存储器请求限制。 结转限制可以指示在预定时间段期间允许的结转存储器请求的最大数量。 新的请求限制可以指示在预定时间段期间允许的新的存储器请求的最大数量。 控制单元还可以控制在预定时间段的序列中的每一个中执行的存储器请求的数量。

公开(公告)号：US5686730A

公开(公告)日：1997-11-11

申请号：US747976

申请日：1996-11-12

申请人： James P. Laudon ,  Daniel E. Lenoski ,  John Manton

发明人： James P. Laudon ,  Daniel E. Lenoski ,  John Manton

IPC分类号： G11C5/00 ,  G11C5/04

CPC分类号： G11C5/06 ,  G11C5/04

摘要： A high memory capacity DIMM for use in a directory-based, distributed shared memory multiprocessor computer system includes a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM is configured for use in a DIMM pair. In the DIMM pair, a first DIMM includes a first data memory having first and second memory bank portions for storing data, and a first state memory configured to store state information corresponding to data stored in a first memory bank. A second DIMM includes a second data memory having third and fourth memory bank portions for storing data, and a second state memory configured to store state information corresponding to data stored in a second memory bank. The first memory bank is formed from the first memory bank portion and the third memory bank portion. The second memory bank is formed from the second memory bank portion and the fourth memory bank portion.

摘要翻译： 用于基于目录的分布式共享存储器多处理器计算机系统中的高存储容量DIMM包括用于存储数据的数据存储器和用于存储对应于数据的至少一部分的状态或目录信息的状态存储器。 DIMM允许独立访问数据和状态信息。 DIMM配置为用于DIMM对。 在DIMM对中，第一DIMM包括具有用于存储数据的第一和第二存储体部分的第一数据存储器，以及配置为存储对应于存储在第一存储体中的数据的状态信息的第一状态存储器。 第二DIMM包括具有用于存储数据的第三和第四存储体部分的第二数据存储器，以及配置为存储对应于存储在第二存储体中的数据的状态信息的第二状态存储器。 第一存储体由第一存储体部分和第三存储体部分形成。 第二存储体由第二存储体部分和第四存储体部分形成。

公开(公告)号：US07574566B2

公开(公告)日：2009-08-11

申请号：US11524837

申请日：2006-09-21

申请人： James P. Laudon

发明人： James P. Laudon

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0837 ,  G06F9/505

摘要： Software-based cache coherence protocol. A processing unit may execute a memory request using a processor thread. In response to detecting a cache hit to shared or a cache miss associated with the memory request, a cache may provide both a trap signal and coherence information to the processor thread of the processing unit. After receiving the trap signal and the coherence information, the processor thread may perform a cache coherence operation for the memory request using at least the received coherence information. The processing unit may include a plurality of processor threads and a load balancer. The load balancer may receive coherence requests from one or more remote processing units and distribute the received coherence requests across the plurality of processor threads. The load balance may preferentially distribute the received coherence requests across the plurality of processor threads based on the operation state of the processor threads.

摘要翻译： 基于软件的缓存一致性协议。 处理单元可以使用处理器线程执行存储器请求。 响应于检测到与存储器请求相关联的共享的缓存命中或高速缓存未命中，高速缓存可以向处理单元的处理器线程提供陷阱信号和一致性信息。 在接收到陷阱信号和相干信息之后，处理器线程可以使用至少所接收的相干信息来执行存储器请求的高速缓存一致性操作。 处理单元可以包括多个处理器线程和负载平衡器。 负载平衡器可以从一个或多个远程处理单元接收一致性请求，并且在多个处理器线程上分发所接收的一致性请求。 基于处理器线程的操作状态，负载平衡可以优先地在多个处理器线程上分配所接收的一致性请求。