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1.发明授权Reduced inductance interconnect for enhanced microwave and millimeter-wave systems 有权用于增强微波和毫米波系统的减少电感互连公开(公告)号：US07528792B2
公开(公告)日：2009-05-05
申请号：US11145889
申请日：2005-06-06
CPC分类号： H01L23/66 , H01L24/83 , H01L2223/6611 , H01L2224/2919 , H01L2224/45014 , H01L2224/48101 , H01L2224/73265 , H01L2224/83851 , H01L2924/01004 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1616 , H01L2924/19051 , H01L2924/30107 , H01L2924/3011 , H01L2924/0665 , H01L2924/00014
摘要： According to one embodiment of the present invention, a microwave or millimeter wave module includes a dielectric layer having a pocket formed substantially through the dielectric layer. The dielectric is attached to a metal substrate. The pocket has substantially vertical sidewalls. An integrated circuit is disposed in the pocket. Opposing sides of the integrated circuit are substantially parallel to the sidewalls of the pocket. An interconnect electrically couples the integrated circuit to a bond pad disposed on the outer surface of the dielectric layer. The interconnect has a length that is minimized to result in reduced inductance of the semiconductor device.
摘要翻译： 根据本发明的一个实施例，微波或毫米波模块包括具有基本上通过介电层形成的口袋的电介质层。 电介质附着在金属基底上。 口袋具有基本垂直的侧壁。 集成电路设置在口袋中。 集成电路的相对侧基本上平行于口袋的侧壁。 互连将集成电路电耦合到设置在电介质层的外表面上的接合焊盘。 互连具有最小化的长度，导致半导体器件的电感降低。
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2.发明申请Reduced Inductance Interconnect for Enhanced Microwave and Millimeter-Wave Systems 有权增强型微波和毫米波系统的降低电感互连公开(公告)号：US20090267235A1
公开(公告)日：2009-10-29
申请号：US12368492
申请日：2009-02-10
IPC分类号： H01L23/535
CPC分类号： H01L23/66 , H01L24/83 , H01L2223/6611 , H01L2224/2919 , H01L2224/45014 , H01L2224/48101 , H01L2224/73265 , H01L2224/83851 , H01L2924/01004 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1616 , H01L2924/19051 , H01L2924/30107 , H01L2924/3011 , H01L2924/0665 , H01L2924/00014
摘要： According to one embodiment of the present invention, a microwave or millimeter wave module includes a dielectric layer having a pocket formed substantially through the dielectric layer. The dielectric is attached to a metal substrate. The pocket has substantially vertical sidewalls. An integrated circuit is disposed in the pocket. Opposing sides of the integrated circuit are substantially parallel to the sidewalls of the pocket. An interconnect electrically couples the integrated circuit to a bond pad disposed on the outer surface of the dielectric layer. The interconnect has a length that is minimized to result in reduced inductance of the semiconductor device.
摘要翻译： 根据本发明的一个实施例，微波或毫米波模块包括具有基本上通过介电层形成的口袋的电介质层。 电介质附着在金属基底上。 口袋具有基本垂直的侧壁。 集成电路设置在口袋中。 集成电路的相对侧基本上平行于口袋的侧壁。 互连将集成电路电耦合到设置在电介质层的外表面上的接合焊盘。 互连具有最小化的长度，导致半导体器件的电感降低。
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3.发明授权Reduced inductance interconnect for enhanced microwave and millimeter-wave systems 有权用于增强微波和毫米波系统的减少电感互连公开(公告)号：US08059057B2
公开(公告)日：2011-11-15
申请号：US12368492
申请日：2009-02-10
CPC分类号： H01L23/66 , H01L24/83 , H01L2223/6611 , H01L2224/2919 , H01L2224/45014 , H01L2224/48101 , H01L2224/73265 , H01L2224/83851 , H01L2924/01004 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1616 , H01L2924/19051 , H01L2924/30107 , H01L2924/3011 , H01L2924/0665 , H01L2924/00014
摘要： According to one embodiment of the present invention, a microwave or millimeter wave module includes a dielectric layer having a pocket formed substantially through the dielectric layer. The dielectric is attached to a metal substrate. The pocket has substantially vertical sidewalls. An integrated circuit is disposed in the pocket. Opposing sides of the integrated circuit are substantially parallel to the sidewalls of the pocket. An interconnect electrically couples the integrated circuit to a bond pad disposed on the outer surface of the dielectric layer. The interconnect has a length that is minimized to result in reduced inductance of the semiconductor device.
摘要翻译： 根据本发明的一个实施例，微波或毫米波模块包括具有基本上通过介电层形成的口袋的电介质层。 电介质附着在金属基底上。 口袋具有基本垂直的侧壁。 集成电路设置在口袋中。 集成电路的相对侧基本上平行于口袋的侧壁。 互连将集成电路电耦合到设置在电介质层的外表面上的接合焊盘。 互连具有最小化的长度，导致半导体器件的电感降低。
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4.发明申请REDUCED INDUCTANCE INTERCONNECT FOR ENHANCED MICROWAVE AND MILLIMETER-WAVE SYSTEMS 有权增强型微波和微波系统的降低电感互连公开(公告)号：US20090085823A1
公开(公告)日：2009-04-02
申请号：US11145889
申请日：2005-06-06
CPC分类号： H01L23/66 , H01L24/83 , H01L2223/6611 , H01L2224/2919 , H01L2224/45014 , H01L2224/48101 , H01L2224/73265 , H01L2224/83851 , H01L2924/01004 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1616 , H01L2924/19051 , H01L2924/30107 , H01L2924/3011 , H01L2924/0665 , H01L2924/00014
摘要： According to one embodiment of the present invention, a microwave or millimeter wave module includes a dielectric layer having a pocket formed substantially through the dielectric layer. The dielectric is attached to a metal substrate. The pocket has substantially vertical sidewalls. An integrated circuit is disposed in the pocket. Opposing sides of the integrated circuit are substantially parallel to the sidewalls of the pocket. An interconnect electrically couples the integrated circuit to a bond pad disposed on the outer surface of the dielectric layer. The interconnect has a length that is minimized to result in reduced inductance of the semiconductor device.
摘要翻译： 根据本发明的一个实施例，微波或毫米波模块包括具有基本上通过介电层形成的口袋的电介质层。 电介质附着在金属基底上。 口袋具有基本垂直的侧壁。 集成电路设置在口袋中。 集成电路的相对侧基本上平行于口袋的侧壁。 互连将集成电路电耦合到设置在电介质层的外表面上的接合焊盘。 互连具有最小化的长度，导致半导体器件的电感降低。
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公开(公告)号：US07840916B2
公开(公告)日：2010-11-23
申请号：US11985966
申请日：2007-11-19
申请人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
发明人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G01R31/2858
摘要： A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltage divider circuit operable to output a plurality of reference voltages having different values. A plurality of comparators in the semiconductor chip may be coupled to receive the reference voltages and a monitored voltage representative of a resistance of the monitored element. Each of the comparators may produce an output indicating whether the monitored voltage exceeds the reference voltages, so that the resistance value of the monitored element may be precisely determined.
摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构可以包括半导体芯片的装置，其可操作以检测半导体芯片的被监测元件的电阻的增加。 该设计结构可以包括例如可操作以输出具有不同值的多个参考电压的电阻分压器电路。 可以将半导体芯片中的多个比较器耦合以接收参考电压和表示所监视元件的电阻的监视电压。 每个比较器可以产生指示监视的电压是否超过参考电压的输出，使得可以精确地确定被监视元件的电阻值。
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6.发明授权公开(公告)号：US07768453B2
公开(公告)日：2010-08-03
申请号：US12188513
申请日：2008-08-08
申请人： James S. Mason , James S. Wilson
发明人： James S. Mason , James S. Wilson
CPC分类号： H01Q3/2605 , H01Q3/267
摘要： Adjusting a calibrated phased array includes receiving conditions data describing conditions at a phased array. The phased array comprises antenna element sets, where an antenna element set comprises antenna elements and is associated with a calibration value. The following is performed for each antenna element set. A temperature value is established for an antenna element set according to the conditions data. A temperature-dependent correction value corresponding to the temperature value is established. A correction value is determined for the antenna element set according to the temperature-dependent correction value and the calibration value associated with the each antenna element set. At least one antenna element of the antenna element set is adjusted according to the correction value.
摘要翻译： 调整校准的相控阵列包括接收描述相控阵列条件的条件数据。 相控阵列包括天线元件组，其中天线元件组包括天线元件并与校准值相关联。 对于每个天线元件组执行以下操作。 根据条件数据为天线元件组建立温度值。 建立对应于温度值的与温度相关的校正值。 根据与温度相关的校正值和与每个天线元件组相关联的校准值，确定天线元件组的校正值。 根据校正值调整天线元件组的至少一个天线元件。
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7.发明申请公开(公告)号：US20100033375A1
公开(公告)日：2010-02-11
申请号：US12188513
申请日：2008-08-08
申请人： James S. Mason , James S. Wilson
发明人： James S. Mason , James S. Wilson
IPC分类号： H01Q3/00
CPC分类号： H01Q3/2605 , H01Q3/267
摘要： Adjusting a calibrated phased array includes receiving conditions data describing conditions at a phased array. The phased array comprises antenna element sets, where an antenna element set comprises antenna elements and is associated with a calibration value. The following is performed for each antenna element set. A temperature value is established for an antenna element set according to the conditions data. A temperature-dependent correction value corresponding to the temperature value is established. A correction value is determined for the antenna element set according to the temperature-dependent correction value and the calibration value associated with the each antenna element set. At least one antenna element of the antenna element set is adjusted according to the correction value.
摘要翻译： 调整校准的相控阵列包括接收描述相控阵列条件的条件数据。 相控阵列包括天线元件组，其中天线元件组包括天线元件并与校准值相关联。 对于每个天线元件组执行以下操作。 根据条件数据为天线元件组建立温度值。 建立对应于温度值的与温度相关的校正值。 根据与温度相关的校正值和与每个天线元件组相关联的校准值，确定天线元件组的校正值。 根据校正值调整天线元件组的至少一个天线元件。
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公开(公告)号：US07659740B2
公开(公告)日：2010-02-09
申请号：US12189226
申请日：2008-08-11
申请人： Joseph O. Marsh , Jeremy Stephens , Charlie C. Hwang , James S. Mason , Huihao Xu , Matthew B. Baecher , Thomas J. Bardsley , Mark R. Taylor
发明人： Joseph O. Marsh , Jeremy Stephens , Charlie C. Hwang , James S. Mason , Huihao Xu , Matthew B. Baecher , Thomas J. Bardsley , Mark R. Taylor
CPC分类号： G01R31/3167 , G01R31/318544
摘要： Digital testing of an analog driver circuit is enabled using a circuit including a control circuit for generating signals, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit, and a differential receiver circuit for converting the differential output signal to a single ended signal and transmitting the single ended signal. The testing includes skewing a differential output termination impedance, adjusting a differential receiver circuit voltage offset, selecting a differential driver circuit power level, enabling a decoder which activates only one differential driver circuit segment per test sequence, activating a segment, stimulating the differential driver circuit with digital test patterns, receiving differential driver circuit output, converting the output to a single-ended signal, and observing the single-ended signal.
摘要翻译： 使用包括用于产生信号的控制电路的电路，用于接收差分输入信号的差分驱动器电路，放大差分输入信号和发送差分输出信号来实现模拟驱动器电路的数字测试，用于产生可编程终端阻抗电路 在差分驱动电路的输出节点处的差分终端阻抗，以及用于将差分输出信号转换为单端信号并发送单端信号的差分接收电路。 测试包括偏移差分输出终端阻抗，调整差分接收器电路电压偏移，选择差分驱动器电路功率电平，使得能够在每个测试序列仅激活一个差分驱动器电路段的解码器，激活段，激励差分驱动器电路 具有数字测试模式，接收差分驱动电路输出，将输出转换为单端信号，并观察单端信号。
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公开(公告)号：US07460077B2
公开(公告)日：2008-12-02
申请号：US11614761
申请日：2006-12-21
申请人： Christian O. Hemmi , James S. Mason
发明人： Christian O. Hemmi , James S. Mason
IPC分类号： H01Q21/00
CPC分类号： H01Q21/061 , H01Q13/085
摘要： In one embodiment, a polarization control system for an antenna array comprises a number of first and second antenna elements and a beam forming network. The first antenna elements have a direction of polarization that is different from a direction of polarization of the second antenna elements. The beam forming network, which is coupled to the first and second antenna elements, is operable to provide a second signal to a first subset of the plurality of first antenna elements that is different from a first signal that is provided to the other first antenna elements and provide a third signal to a second subset of the second antenna elements that is different from the first signal that is provided to the other second antenna elements.
摘要翻译： 在一个实施例中，用于天线阵列的偏振控制系统包括多个第一和第二天线元件以及波束形成网络。 第一天线元件具有不同于第二天线元件的极化方向的偏振方向。 耦合到第一和第二天线元件的波束形成网络可操作以向多个第一天线元件的第一子集提供不同于提供给其它第一天线元件的第一信号的第二信号 并向第二天线元件的第二子集提供不同于提供给其它第二天线元件的第一信号的第三信号。
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公开(公告)号：US07456789B1
公开(公告)日：2008-11-25
申请号：US11101703
申请日：2005-04-08
IPC分类号： H01Q1/38
摘要： According to an embodiment of the present invention, a multi-function carrier structure for a phased array radar includes a substrate that includes a mounting surface for a plurality of transmit/receive modules, a plurality of radiating elements integrally formed in the substrate adjacent the mounting surface, and a plurality of cooling channels integrally formed within a thickness of the substrate. The substrate is formed from a material having a coefficient of thermal expansion similar to respective substrates of the transmit/receive modules.
摘要翻译： 根据本发明的实施例，用于相控阵雷达的多功能载波结构包括：基板，其包括用于多个发射/接收模块的安装表面;多个辐射元件，其一体地形成在所述基板中， 表面，以及在基板的厚度内整体形成的多个冷却通道。 衬底由具有类似于发射/接收模块的各个衬底的热膨胀系数的材料形成。
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