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    FULLY-DEPLETED LOW-BODY DOPING FIELD EFFECT TRANSISTOR (FET) WITH REVERSE SHORT CHANNEL EFFECTS (SCE) INDUCED BY SELF-ALIGNED EDGE BACK-GATE(S)
    1.
    发明申请
    FULLY-DEPLETED LOW-BODY DOPING FIELD EFFECT TRANSISTOR (FET) WITH REVERSE SHORT CHANNEL EFFECTS (SCE) INDUCED BY SELF-ALIGNED EDGE BACK-GATE(S) 有权
    具有反向短路通道效应（SCE）的全自动低体积场效应晶体管（FET）由自对准边缘背栅（S）

    公开(公告)号：US20090261415A1

    公开(公告)日：2009-10-22

    申请号：US12104683

    申请日：2008-04-17

    申请人： James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    发明人： James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    IPC分类号： H01L49/00 ,  H01L21/00

    CPC分类号： H01L29/78603 ,  H01L29/66621 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78696

    摘要： Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source/drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and/or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs.

    摘要翻译： 公开了场效应晶体管（FET）的具体实施例，更具体地说，是允许以最小的短沟道效应（例如漏极感应势垒降低（DIBL）和饱和阈值））进行缩放的完全耗尽的薄体（FDTB）FET 电压（Vtsat）滚降，通道长度较短。 FDTB FET实施例配置有可被偏置的边缘背栅极或分支反向栅极，以便选择性地调节源极/漏极区域和沟道区域之间的势垒，以最小化漏极之间的截止状态漏电流 区域和源极区域和/或用于改变阈值电压。 这些独特的背栅结构避免了对光晕掺杂的需要，以确保较小通道长度的线性阈值电压（Vtlin）汇总，从而避免由于随机掺杂波动引起的跨芯片阈值电压变化。 还公开了用于形成这种FET的方法实施例。

    Fully-depleted low-body doping field effect transistor (FET) with reverse short channel effects (SCE) induced by self-aligned edge back-gate(s)
    2.
    发明授权
    Fully-depleted low-body doping field effect transistor (FET) with reverse short channel effects (SCE) induced by self-aligned edge back-gate(s) 有权
    具有由自对准边缘后栅极引起的反向短沟道效应（SCE）的全耗尽低体积掺杂场效应晶体管（FET）

    公开(公告)号：US07943997B2

    公开(公告)日：2011-05-17

    申请号：US12104683

    申请日：2008-04-17

    申请人： James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Edward J. Nowak

    发明人： James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Edward J. Nowak

    IPC分类号： H01L27/12

    CPC分类号： H01L29/78603 ,  H01L29/66621 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78696

    摘要： Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source/drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and/or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs.

    摘要翻译： 公开了场效应晶体管（FET）的具体实施例，更具体地说，是允许以最小的短沟道效应（例如漏极感应势垒降低（DIBL）和饱和阈值））进行缩放的完全耗尽的薄体（FDTB）FET 电压（Vtsat）滚降，通道长度较短。 FDTB FET实施例配置有可被偏置的边缘背栅极或分支反向栅极，以便选择性地调节源极/漏极区域和沟道区域之间的势垒，以最小化漏极之间的截止状态漏电流 区域和源极区域和/或用于改变阈值电压。 这些独特的背栅结构避免了对光晕掺杂的需要，以确保较小通道长度的线性阈值电压（Vtlin）汇总，从而避免由于随机掺杂波动引起的跨芯片阈值电压变化。 还公开了用于形成这种FET的方法实施例。

    CONTACT BARS FOR MODIFYING STRESS IN SEMICONDUCTOR DEVICE AND RELATED METHOD
    3.
    发明申请
    CONTACT BARS FOR MODIFYING STRESS IN SEMICONDUCTOR DEVICE AND RELATED METHOD 审中-公开
    用于修改半导体器件中的应力的接触棒及相关方法

    公开(公告)号：US20130240997A1

    公开(公告)日：2013-09-19

    申请号：US13424319

    申请日：2012-03-19

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    IPC分类号： H01L27/11 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L27/1104 ,  H01L29/7843

    摘要： Solutions for forming stress optimizing contact bars and contacts are disclosed. In one aspect, a semiconductor device is disclosed including an n-type field effect transistor (NFET) having source/drain regions; a p-type field effect transistor (PFET) having source/drain regions; a stress inducing layer over both the NFET and the PFET, the stress inducing layer inducing only one of a compressive stress and a tensile stress; a contact bar extending through the stress inducing layer and coupled to at least one of the source/drain regions of a selected device of the PFET and the NFET to modify a stress induced in the selected device compared to a stress induced in the other device; and a round contact extending through the stress inducing layer and coupled to at least one of the source/drain regions of the other device of the PFET and the NFET.

    摘要翻译： 公开了用于形成应力优化接触棒和触点的解决方案。 一方面，公开了一种具有源极/漏极区域的n型场效应晶体管（NFET）的半导体器件; 具有源极/漏极区域的p型场效应晶体管（PFET） 在NFET和PFET两者上的应力诱导层，应力诱导层仅引起压缩应力和拉伸应力之一; 接触棒延伸穿过应力感应层并且耦合到PFET和NFET的所选器件的源/漏区中的至少一个，以修改与在另一器件中感应的应力相比在所选器件中感应的应力; 以及延伸穿过应力感应层并且耦合到PFET和NFET的另一个器件的源极/漏极区域中的至少一个的圆形接触。

    ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
    6.
    发明申请
    ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 有权
    不对称场效应晶体管结构与方法

    公开(公告)号：US20090020806A1

    公开(公告)日：2009-01-22

    申请号：US11778185

    申请日：2007-07-16

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/76

    CPC分类号： H01L29/0847 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7835

    摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).

    摘要翻译： 公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供 改进的驱动电流，电路延迟最小）。 具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻 值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定电容值）。

    Low capacitance FET for operation at subthreshold voltages
    7.
    发明授权
    Low capacitance FET for operation at subthreshold voltages 有权
    低电容FET，用于在亚阈值电压下工作

    公开(公告)号：US07009265B2

    公开(公告)日：2006-03-07

    申请号：US10710007

    申请日：2004-06-11

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Edward J. Nowak

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/7833 ,  H01L29/1045 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/7835 ,  H01L29/785

    摘要： A field effect transistor (FET) has underlap regions adjacent to the channel doping region. The underlap regions have very low dopant concentrations of less than 1×1017/cc or 5×1016/cc and so tend to have a high resistance. The underlap regions reduce overlap capacitance and thereby increase switching speed. High resistance of the underlap regions is not problematic at subthreshold voltages because the channel doping region also has a high resistance at subthreshold voltages. Consequently, the present FET has low capacitance and high speed and is particularly well suited for operation in the subthreshold regime.

    摘要翻译： 场效应晶体管（FET）具有与沟道掺杂区域相邻的底部区域。 底层区域具有小于1×10 17 / cc或5×10 16 / cc的非常低的掺杂剂浓度，因此倾向于具有高电阻。 下层区域减少重叠电容，从而提高开关速度。 欠电压区域的高电阻在亚阈值电压下是没有问题的，因为沟道掺杂区域在亚阈值电压下也具有高电阻。 因此，本FET具有低电容和高速度，并且特别适合于在亚阈值状态下操作。

    Pixel sensor cell with a dual work function gate electrode
    8.
    发明授权
    Pixel sensor cell with a dual work function gate electrode 有权
    具有双功能栅极电极的像素传感器单元

    公开(公告)号：US08580601B2

    公开(公告)日：2013-11-12

    申请号：US13571986

    申请日：2012-08-10

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  John Joseph Ellis-Monaghan ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  John Joseph Ellis-Monaghan ,  Edward J. Nowak

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14614

    摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.

    摘要翻译： 像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。 像素传感器单元具有在栅极电介质上包括栅极电介质和栅电极的栅极结构。 栅极电极包括具有在栅极电介质上具有并置关系的第一和第二部分的层。 栅电极的第二部分由诸如掺杂多晶硅或金属的导体组成。 栅电极的第一部分由具有比包括第二部分的导体更高的功函的金属组成，使得栅极结构具有非对称阈值电压。

    ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
    10.
    发明申请
    ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 有权
    不对称场效应晶体管结构与方法

    公开(公告)号：US20120168832A1

    公开(公告)日：2012-07-05

    申请号：US13246175

    申请日：2011-09-27

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    IPC分类号： H01L29/78

    CPC分类号： H01L29/0847 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7835

    摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).

    摘要翻译： 公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供 改进的驱动电流，电路延迟最小）。 具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻 值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。