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    Multiple precipitation doping process
    1.
    发明授权
    Multiple precipitation doping process 失效
    多重沉淀掺杂工艺

    公开(公告)号：US06300228B1

    公开(公告)日：2001-10-09

    申请号：US09386089

    申请日：1999-08-30

    申请人： James W. Adkisson ,  James A. Bruce ,  John J. Ellis-Monaghan ,  Randy W. Mann ,  Edward J. Nowak ,  Kirk D. Peterson

    发明人： James W. Adkisson ,  James A. Bruce ,  John J. Ellis-Monaghan ,  Randy W. Mann ,  Edward J. Nowak ,  Kirk D. Peterson

    IPC分类号： H01L2122

    CPC分类号： H01L21/268 ,  H01L21/0455 ,  H01L21/2255

    摘要： A multiple precipitation doping process for doping a semiconductor substrate (30) starts with forming an amorphous region (32) in the substrate (30). Through multiple laser exposures, multiple dopant precipitation films (52, 53) are formed on corresponding portions (34, 37) of the major surface (31) of the substrate (30) overlying the amorphous region (32). The substrate (30) is then annealed. The annealing process melts the amorphous region (32) and allows the dopants precipitated on the major surface (31) to diffuse into the substrate (30). The annealing process also crystallizes the semiconductor material the amorphous region (32). The substrate (30) becomes a single crystal semiconductor substrate with multiple doped regions (54, 57) therein. The depth of the doped regions (54, 57) is substantially equal to the depth of the amorphous region (32) before annealing.

    摘要翻译： 用于掺杂半导体衬底（30）的多次沉淀掺杂工艺从在衬底（30）中形成无定形区域（32）开始。 通过多次激光曝光，在覆盖非晶区域（32）的衬底（30）的主表面（31）的相应部分（34,37）上形成多个掺杂剂沉淀膜（52,53）。 然后将衬底（30）退火。 退火过程熔化非晶区域（32）并且允许沉淀在主表面（31）上的掺杂剂扩散到衬底（30）中。 退火过程也使非晶区域（32）半导体材料结晶。 基板（30）成为具有多个掺杂区域（54,57）的单晶半导体基板。 掺杂区域（54,57）的深度基本上等于退火前非晶区域（32）的深度。

    3-DIMENSIONAL INTEGRATED CIRCUIT TESTING USING MEMS SWITCHES WITH TUNGSTEN CONE CONTACTS
    5.
    发明申请
    3-DIMENSIONAL INTEGRATED CIRCUIT TESTING USING MEMS SWITCHES WITH TUNGSTEN CONE CONTACTS 有权
    采用微机电开关的三维集成电路测试

    公开(公告)号：US20130200910A1

    公开(公告)日：2013-08-08

    申请号：US13364345

    申请日：2012-02-02

    申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    IPC分类号： G01R1/067 ,  H01L21/768

    CPC分类号： G01R1/06727 ,  B81B2203/0118 ,  B81C1/00111 ,  G01R1/06738 ,  G01R1/06744 ,  G01R1/07342 ,  G01R3/00 ,  H01L21/76804 ,  H01L21/76885 ,  H01L22/14 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A test system for testing a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality, includes a chip under test with a first portion of the 3-dimensional IC, and a test probe chip with a second portion of the 3-dimensional IC and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits between the first portion of the 3-dimensional IC in a first IC layer to circuits within the second portion of the 3-dimensional IC in a second IC layer. The MEMS switches include tungsten (W) cone contacts, which make the selective electrical contacts between circuits of the chip under test and the test probe chip and which are formed using a template of graded borophosphosilicate glass (BPSG).

    摘要翻译： 一种用于测试多层三维集成电路（IC）的测试系统，其中临时连接两个独立的IC电路层以实现功能性，包括具有三维IC的第一部分的被测芯片，以及 测试探针芯片，其具有第三部分的IC和微机电系统（MEMS）开关，其选择性地完成第一IC层中的第三部分的第三部分之间的功能电路和第二部分内的电路 的三维IC在第二IC层中。 MEMS开关包括钨（W）锥形触点，其使得被测芯片的电路和测试探针芯片之间的选择性电接触，并且使用梯度硼磷硅酸盐玻璃（BPSG）的模板形成。

    Nitride etch for improved spacer uniformity
    6.
    发明授权
    Nitride etch for improved spacer uniformity 失效
    氮化物蚀刻用于改善间隔物均匀性

    公开(公告)号：US08470713B2

    公开(公告)日：2013-06-25

    申请号：US12966432

    申请日：2010-12-13

    申请人： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Christa R. Willets

    发明人： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Christa R. Willets

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31116 ,  H01L21/28035 ,  H01L21/76237 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/78

    摘要： A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.

    摘要翻译： 一种形成电介质间隔物的方法，包括提供包括具有第一多个栅极结构的第一区域和具有第二多个栅极结构的第二区域和至少一种含氧化物的材料或含碳材料的衬底。 在第一区域上形成厚度小于存在于第二区域中的含氮化物层的厚度的含氮化物层。 在第一多个第二多个栅极结构上从氮化物含有层形成电介质间隔物。 所述至少一种含氧化物的材料或含碳材料加速了第二区域中的蚀刻，使得第一区域中的电介质间隔物的厚度基本上等于衬底的第二区域中的电介质间隔物的厚度。

    Variable Focus Point Lens
    7.
    发明申请
    Variable Focus Point Lens 有权
    可变焦点镜头

    公开(公告)号：US20110208482A1

    公开(公告)日：2011-08-25

    申请号：US12708561

    申请日：2010-02-19

    申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    IPC分类号： G06F17/50 ,  G02B3/12

    CPC分类号： G02B3/14

    摘要： A variable focal point lens includes a transparent tank, which comprises a transparent enclosure containing a transparent flexible membrane separating the inner volume of the transparent tank into an upper tank portion and a lower tank portion. The upper tank portion and the lower tank portion contain liquids having different indices of refraction. The transparent flexible membrane is electrostatically displaced to change the thicknesses of the first tank portion and the second tank portion in the path of the light, thereby shifting the focal point of the lens axially and/or laterally. The electrostatic displacement of the membrane may be effected by a fixed charge in the membrane and an array of enclosure-side conductive structures on the transparent enclosure, or an array of membrane-side conductive structures on the transparent membrane and an array of enclosure-side conductive structures.

    摘要翻译： 可变焦点透镜包括透明容器，透明容器包括透明的外壳，该透明外壳包含将透明容器的内部容积分隔成上部容器部分和下部容器部分的透明柔性膜。 上罐部分和下罐部分含有不同折射率的液体。 透明柔性膜被静电移位以改变光路中的第一罐部分和第二罐部分的厚度，从而轴向和/或横向地移动透镜的焦点。 膜的静电位移可以通过膜中的固定电荷和透明外壳上的封闭侧导电结构阵列，或透明膜上的膜侧导电结构阵列和外壳侧阵列 导电结构。

    High dynamic range imaging cell with electronic shutter extensions
    8.
    发明授权
    High dynamic range imaging cell with electronic shutter extensions 有权
    具有电子快门延伸功能的高动态范围成像单元

    公开(公告)号：US07948535B2

    公开(公告)日：2011-05-24

    申请号：US11948463

    申请日：2007-11-30

    申请人： John J. Ellis-Monaghan ,  Alain Loiseau ,  Kirk D. Peterson

    发明人： John J. Ellis-Monaghan ,  Alain Loiseau ,  Kirk D. Peterson

    IPC分类号： H04N3/14 ,  H04N5/335

    CPC分类号： H04N5/37452 ,  H04N5/35527 ,  H04N5/3559

    摘要： A pixel sensor cell of improved dynamic range and a design structure including the pixel sensor cell embodied in a machine readable medium are provided. The pixel cell comprises a coupling transistor that couples a capacitor device to a photosensing region (e.g., photodiode) of the pixel cell, the photodiode being coupled to a transfer gate and one terminal of the coupling transistor. In operation, the additional capacitance is coupled to the pixel cell photodiode when the voltage on the photodiode is drawn down to the substrate potential. Thus, the added capacitance is only connected to the imager cell when the cell is nearing its charge capacity. Otherwise, the cell has a low capacitance and low leakage. In an additional embodiment, a terminal of the capacitor is coupled to a “pulsed” supply voltage signal that enables substantially full depletion of stored charge from the capacitor to the photosensing region during a read out operation of the pixel sensor cell. In various embodiments, the locations of the added capacitance and photodiode may be interchanged with respect to the coupling transistor. In addition, the added capacitor of the pixel sensor cell allows for a global shutter operation.

    摘要翻译： 提供了改进的动态范围的像素传感器单元和包括体现在机器可读介质中的像素传感器单元的设计结构。 像素单元包括将电容器器件耦合到像素单元的光敏区域（例如，光电二极管）的耦合晶体管，光电二极管耦合到传输栅极和耦合晶体管的一个端子。 在操作中，当光电二极管上的电压向下拉到衬底电位时，附加电容耦合到像素单元光电二极管。 因此，当电池接近其充电容量时，所添加的电容仅连接到成像器单元。 否则，电池具有低电容和低泄漏。 在另外的实施例中，电容器的端子耦合到“脉冲”电源电压信号，其在像素传感器单元的读出操作期间使存储的电荷从电容器到光敏区域基本上完全耗尽。 在各种实施例中，增加的电容和光电二极管的位置可以相对于耦合晶体管互换。 此外，像素传感器单元的附加电容允许全局快门操作。

    SYSTEM AND METHOD FOR CORRECTING SYSTEMATIC PARAMETRIC VARIATIONS ON INTEGRATED CIRCUIT CHIPS IN ORDER TO MINIMIZE CIRCUIT LIMITED YIELD LOSS
    9.
    发明申请
    SYSTEM AND METHOD FOR CORRECTING SYSTEMATIC PARAMETRIC VARIATIONS ON INTEGRATED CIRCUIT CHIPS IN ORDER TO MINIMIZE CIRCUIT LIMITED YIELD LOSS 有权
    用于校正集成电路芯片的系统参数变化的系统和方法，以最小化电路有限的损失

    公开(公告)号：US20110098838A1

    公开(公告)日：2011-04-28

    申请号：US12603679

    申请日：2009-10-22

    申请人： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    发明人： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/10

    摘要： Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized.

    摘要翻译： 公开了一种用于校正集成电路芯片上的系统的，基于设计的参数变化的系统和方法，以最小化电路限制的产量损失。 存储处理信息和芯片的映射。 处理信息可以指示给定设备参数对与给定过程步骤相关联的规范的值的变化的影响。 地图可以指示设备参数中的区域变化（例如，阈值电压）。 基于处理信息并使用该图作为指导，确定规范的不同值，每个值在处理步骤期间应用于集成电路芯片的不同区域，以便抵消映射的区域参数变化。 然后可以选择性地控制处理工具，以确保在芯片制造期间相应地执行工艺步骤，从而确保区域参数变化最小化。

    Halo implant in semiconductor structures
    10.
    发明授权
    Halo implant in semiconductor structures 失效
    半导体结构中的光晕植入物

    公开(公告)号：US06949796B1

    公开(公告)日：2005-09-27

    申请号：US10711484

    申请日：2004-09-21

    申请人： John J. Ellis-Monaghan ,  Kirk D. Peterson ,  Jeffrey S. Zimmerman

    发明人： John J. Ellis-Monaghan ,  Kirk D. Peterson ,  Jeffrey S. Zimmerman

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/76

    CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/1083

    摘要： A halo implant method for forming halo regions of at least first and second transistors formed on a same semiconductor substrate. The first transistor comprises a first gate region disposed between first and second semiconductor regions. The second transistor comprises a second gate region disposed between third and fourth semiconductor regions. The method comprises the steps of, in turn, halo-implanting each of the first, second, third, and fourth semiconductor regions, with the other three semiconductor regions being masked, in a projected direction which (i) is essentially perpendicular to the direction of the respective gate region and (ii) points from the halo-implanted semiconductor region to the respective gate region.

    摘要翻译： 一种用于形成在同一半导体衬底上的至少第一和第二晶体管的晕圈的光晕注入方法。 第一晶体管包括设置在第一和第二半导体区域之间的第一栅极区域。 第二晶体管包括设置在第三和第四半导体区域之间的第二栅极区域。 该方法包括以下步骤：依次在投影方向上将第一，第二，第三和第四半导体区域中的每一个卤素注入，其他三个半导体区域被掩蔽，其中（i）基本上垂直于方向 和（ii）从注入卤素的半导体区到相应的栅极区的点。