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公开(公告)号：US06949796B1
公开(公告)日：2005-09-27
申请号：US10711484
申请日：2004-09-21
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L29/10 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L29/1083
摘要： A halo implant method for forming halo regions of at least first and second transistors formed on a same semiconductor substrate. The first transistor comprises a first gate region disposed between first and second semiconductor regions. The second transistor comprises a second gate region disposed between third and fourth semiconductor regions. The method comprises the steps of, in turn, halo-implanting each of the first, second, third, and fourth semiconductor regions, with the other three semiconductor regions being masked, in a projected direction which (i) is essentially perpendicular to the direction of the respective gate region and (ii) points from the halo-implanted semiconductor region to the respective gate region.
摘要翻译： 一种用于形成在同一半导体衬底上的至少第一和第二晶体管的晕圈的光晕注入方法。 第一晶体管包括设置在第一和第二半导体区域之间的第一栅极区域。 第二晶体管包括设置在第三和第四半导体区域之间的第二栅极区域。 该方法包括以下步骤：依次在投影方向上将第一，第二，第三和第四半导体区域中的每一个卤素注入，其他三个半导体区域被掩蔽，其中（i）基本上垂直于方向 和（ii）从注入卤素的半导体区到相应的栅极区的点。
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2.发明申请STRUCTURE, SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE AND PACKAGING THEREOF 审中-公开结构，半导体结构及制造半导体结构及其包装的方法公开(公告)号：US20120104600A1
公开(公告)日：2012-05-03
申请号：US13344628
申请日：2012-01-06
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/13 , H01L2224/0401 , H01L2224/05006 , H01L2224/05093 , H01L2224/05567 , H01L2224/05571 , H01L2224/10122 , H01L2224/10126 , H01L2224/13006 , H01L2224/13022 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2224/05552
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.
摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括在设计敏感结构和钝化层之间形成的电介质材料。 该设计敏感结构包括通过通孔连接器电连接和机械地连接到更高布线层的下布线层。 还提供了一种方法和结构。
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3.发明授权公开(公告)号：US08114767B2
公开(公告)日：2012-02-14
申请号：US12046616
申请日：2008-03-12
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
IPC分类号： H01L21/4763
CPC分类号： H01L24/05 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/13 , H01L2224/0401 , H01L2224/05006 , H01L2224/05093 , H01L2224/05567 , H01L2224/05571 , H01L2224/10122 , H01L2224/10126 , H01L2224/13006 , H01L2224/13022 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2224/05552
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.
摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括在设计敏感结构和钝化层之间形成的电介质材料。 该设计敏感结构包括通过通孔连接器电连接和机械地连接到更高布线层的下布线层。 还提供了一种方法和结构。
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公开(公告)号：US08990478B2
公开(公告)日：2015-03-24
申请号：US13555412
申请日：2012-07-23
摘要： Aspects of the invention provide for masking a current profile of a one-time programmable (OTP) memory. In one embodiment, a circuit includes: a first one-time programmable (OTP) memory configured to receive a data input for a plurality of address fields; and a second OTP memory configured to receive an inverse of the data input for a plurality of address fields, wherein a current profile for a programming supply for the first OTP memory and the second OTP memory is masked, such that the data input for the first OTP memory is undetectable.
摘要翻译： 本发明的方面提供了掩蔽一次性可编程（OTP）存储器的当前简档。 在一个实施例中，电路包括：被配置为接收多个地址字段的数据输入的第一一次可编程（OTP）存储器; 以及第二OTP存储器，被配置为接收对于多个地址字段的数据输入的反相，其中屏蔽用于第一OTP存储器和第二OTP存储器的编程电源的当前简档，使得为第一 OTP内存不可检测。
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5.发明申请公开(公告)号：US20090246892A1
公开(公告)日：2009-10-01
申请号：US12056627
申请日：2008-03-27
IPC分类号： H01L21/66 , H01L23/58 , H01L23/544
CPC分类号： H01L23/585 , H01L22/34 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： The invention generally relates to a design structure of a circuit design, and more particularly to a design structure of a delamination sensor for use with low-k materials. A delamination sensor includes at least one first sensor formed in a layered semiconductor structure and a second sensor formed in the layered semiconductor structure. The at least one first sensor is structured and arranged to detect a defect, and the second sensor is structured and arranged to identify an interface where the defect exists.
摘要翻译： 本发明一般涉及一种电路设计的设计结构，更具体地说，涉及一种用于低k材料的分层传感器的设计结构。 分层传感器包括形成在层状半导体结构中的至少一个第一传感器和形成在层状半导体结构中的第二传感器。 所述至少一个第一传感器被构造和布置成检测缺陷，并且所述第二传感器被构造和布置成识别存在缺陷的界面。
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6.发明申请公开(公告)号：US20090230547A1
公开(公告)日：2009-09-17
申请号：US12046616
申请日：2008-03-12
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
CPC分类号： H01L24/05 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/13 , H01L2224/0401 , H01L2224/05006 , H01L2224/05093 , H01L2224/05567 , H01L2224/05571 , H01L2224/10122 , H01L2224/10126 , H01L2224/13006 , H01L2224/13022 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2224/05552
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.
摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括在设计敏感结构和钝化层之间形成的电介质材料。 该设计敏感结构包括通过通孔连接器电连接和机械地连接到更高布线层的下布线层。 还提供了一种方法和结构。
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7.发明申请STRUCTURE AND METHOD FOR REDUCING SUSCEPTIBILITY TO CHARGING DAMAGE IN SOI DESIGNS 审中-公开用于降低SOI设计中对充电损害的可靠性的结构和方法公开(公告)号：US20070271540A1
公开(公告)日：2007-11-22
申请号：US11383565
申请日：2006-05-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , H01L27/0251
摘要： Disclosed is a protection circuit for an integrated circuit device, wherein said protection circuit comprises: a first element connected to a gate of a first FET device; and a second element connected to a gate of a second FET device, wherein a drain/source of the first FET device and a drain/source of the second FET device are connected to a higher level connector and wherein the higher level connector eliminates a damaging current path between the first element and the second element.
摘要翻译： 公开了一种用于集成电路器件的保护电路，其中所述保护电路包括：连接到第一FET器件的栅极的第一元件; 以及连接到第二FET器件的栅极的第二元件，其中所述第一FET器件的漏极/源极和所述第二FET器件的漏极/源极连接到较高级别的连接器，并且其中所述较高级连接器消除了损坏 第一元件和第二元件之间的电流路径。
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公开(公告)号：US20140025915A1
公开(公告)日：2014-01-23
申请号：US13555412
申请日：2012-07-23
IPC分类号： G06F12/14
摘要： Aspects of the invention provide for masking a current profile of a one-time programmable (OTP) memory. In one embodiment, a circuit includes: a first one-time programmable (OTP) memory configured to receive a data input for a plurality of address fields; and a second OTP memory configured to receive an inverse of the data input for a plurality of address fields, wherein a current profile for a programming supply for the first OTP memory and the second OTP memory is masked, such that the data input for the first OTP memory is undetectable.
摘要翻译： 本发明的方面提供了掩蔽一次性可编程（OTP）存储器的当前简档。 在一个实施例中，电路包括：被配置为接收多个地址字段的数据输入的第一一次可编程（OTP）存储器; 以及第二OTP存储器，被配置为接收对于多个地址字段的数据输入的反相，其中屏蔽用于第一OTP存储器和第二OTP存储器的编程电源的当前简档，使得为第一 OTP内存不可检测。
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9.发明授权Structure, failure analysis tool and method of determining white bump location using failure analysis tool 有权使用故障分析工具确定白色凹凸位置的结构，故障分析工具和方法公开(公告)号：US07958477B2
公开(公告)日：2011-06-07
申请号：US12046608
申请日：2008-03-12
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
CPC分类号： G06F17/5081
摘要： A failure analysis tool, a method of using the tool and a design structure for designing a mask for protecting a critical area of wiring failure in a semiconductor chip during packaging is provided. The failure analysis tool includes a computer infrastructure operable to determine a risk area for wiring layer failure during solder bump formation by determining a distance from a center of a chip to a location for a solder bump processing and identifying an area at an edge of the location for the solder bump processes at a predetermined distance and greater from the center of the chip.
摘要翻译： 提供了故障分析工具，使用该工具的方法和设计用于设计用于保护封装期间半导体芯片中的接线故障的关键区域的掩模的设计结构。 故障分析工具包括计算机基础设施，其可操作以通过确定从芯片的中心到焊料凸块处理的位置的距离来确定在焊料凸块形成期间的布线层故障的风险区域，并且识别位置边缘处的区域 用于从芯片的中心预定距离和更大的焊料凸块工艺。
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10.发明授权公开(公告)号：US07716992B2
公开(公告)日：2010-05-18
申请号：US12056627
申请日：2008-03-27
IPC分类号： G01B7/16
CPC分类号： H01L23/585 , H01L22/34 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： The invention generally relates to a design structure of a circuit design, and more particularly to a design structure of a delamination sensor for use with low-k materials. A delamination sensor includes at least one first sensor formed in a layered semiconductor structure and a second sensor formed in the layered semiconductor structure. The at least one first sensor is structured and arranged to detect a defect, and the second sensor is structured and arranged to identify an interface where the defect exists.
摘要翻译： 本发明一般涉及一种电路设计的设计结构，更具体地说，涉及一种用于低k材料的分层传感器的设计结构。 分层传感器包括形成在层状半导体结构中的至少一个第一传感器和形成在层状半导体结构中的第二传感器。 所述至少一个第一传感器被构造和布置成检测缺陷，并且所述第二传感器被构造和布置成识别存在缺陷的界面。
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