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1.发明授权公开(公告)号：US08375241B2
公开(公告)日：2013-02-12
申请号：US12417534
申请日：2009-04-02
CPC分类号： G06F1/04 , G11C7/1045 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.
摘要翻译： 一种改善注册内存模块操作的方法和系统。 在本发明的一个实施例中，当登记的存储器模块中的时钟电路被激活时，所登记的存储器模块允许异步读取和写入操作。 在本发明的另一个实施例中，登记的存储器模块允许其时钟电路的启用或禁用，而不会中断其操作。 当注册的存储器模块中的时钟电路被禁用时，可以减少注册的存储器模块的功耗。 在本发明的另一实施例中，允许登记的存储器模块进入或退出异步操作模式，而不进入或退出已注册存储器模块的自刷新或预充电掉电操作模式。
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2.发明申请公开(公告)号：US20130145197A1
公开(公告)日：2013-06-06
申请号：US13741532
申请日：2013-01-15
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , G11C7/1045 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.
摘要翻译： 一种改善注册内存模块操作的方法和系统。 在本发明的一个实施例中，当登记的存储器模块中的时钟电路被激活时，所登记的存储器模块允许异步读取和写入操作。 在本发明的另一个实施例中，登记的存储器模块允许其时钟电路的启用或禁用，而不会中断其操作。 当注册的存储器模块中的时钟电路被禁用时，可以减少注册的存储器模块的功耗。 在本发明的另一实施例中，允许登记的存储器模块进入或退出异步操作模式，而不进入或退出已注册存储器模块的自刷新或预充电掉电操作模式。
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3.发明申请公开(公告)号：US20100257398A1
公开(公告)日：2010-10-07
申请号：US12417534
申请日：2009-04-02
IPC分类号： G06F1/12
CPC分类号： G06F1/04 , G11C7/1045 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.
摘要翻译： 一种改善注册内存模块操作的方法和系统。 在本发明的一个实施例中，当登记的存储器模块中的时钟电路被激活时，所登记的存储器模块允许异步读取和写入操作。 在本发明的另一个实施例中，登记的存储器模块允许其时钟电路的启用或禁用，而不会中断其操作。 当注册的存储器模块中的时钟电路被禁用时，可以减少注册的存储器模块的功耗。 在本发明的另一实施例中，允许登记的存储器模块进入或退出异步操作模式，而不进入或退出已注册存储器模块的自刷新或预充电掉电操作模式。
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4.发明授权公开(公告)号：US08661284B2
公开(公告)日：2014-02-25
申请号：US13741532
申请日：2013-01-15
CPC分类号： G06F1/04 , G11C7/1045 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.
摘要翻译： 一种改善注册内存模块操作的方法和系统。 在本发明的一个实施例中，当登记的存储器模块中的时钟电路被激活时，所登记的存储器模块允许异步读取和写入操作。 在本发明的另一个实施例中，登记的存储器模块允许其时钟电路的启用或禁用，而不会中断其操作。 当注册的存储器模块中的时钟电路被禁用时，可以减少注册的存储器模块的功耗。 在本发明的另一实施例中，允许登记的存储器模块进入或退出异步操作模式，而不进入或退出已注册存储器模块的自刷新或预充电掉电操作模式。
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公开(公告)号：US09442871B2
公开(公告)日：2016-09-13
申请号：US13995477
申请日：2011-12-22
申请人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
发明人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
CPC分类号： G11C7/1072 , G06F11/073 , G06F11/0787 , G06F11/10 , G06F11/1004 , G06F11/1016 , G06F11/1612 , G06F13/16 , G06F13/28 , G11C7/1006 , G11C29/44 , G11C2029/0411 , G11C2029/4402
摘要： A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.
摘要翻译： 通过将地址总线上的数据传送到连接到数据总线的设备，可以读取未连接到数据总线的寄存器，数据由连接到数据总线的设备读取。 寄存器位于通过地址总线连接到连接到地址总线和数据总线两者的存储器件的寄存器中。 主处理器触发寄存器设备通过地址总线将信息传送到存储器设备上的寄存器。 然后主机处理器从存储器件的寄存器读取信息。
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6.发明申请METHOD, APPARATUS AND SYSTEM TO MANAGE IMPLICIT PRE-CHARGE COMMAND SIGNALING 有权方法，装置和系统来管理隐式预充电指令信号公开(公告)号：US20160093344A1
公开(公告)日：2016-03-31
申请号：US14498509
申请日：2014-09-26
IPC分类号： G11C7/10
CPC分类号： G11C7/1072 , G06F13/1668 , G06F13/1689 , G06F21/79 , G11C7/1045 , G11C7/1048 , G11C7/1063 , G11C7/109 , G11C11/4076 , G11C11/4093 , G11C11/4094 , Y02D10/14
摘要： Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number.
摘要翻译： 用于在存储器控制器和存储器件之间交换信息的技术和机制。 在一个实施例中，存储器控制器接收指示存储器设备访问该存储器设备的临时统一激活命令的阈值数量的信息。 由信息指示的阈值数小于待处理的合并激活命令的理论最大数量，基于存储器件的定时参数定义的理论最大数量。 在另一个实施例中，存储器控制器基于指示阈值数量的信息来限制合并的激活命令到存储器设备的通信。
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公开(公告)号：US09053812B2
公开(公告)日：2015-06-09
申请号：US13533476
申请日：2012-06-26
申请人： Kuljit S. Bains
发明人： Kuljit S. Bains
IPC分类号： G06F12/00 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/4076 , G11C2211/4067
摘要： Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.
摘要翻译： 本发明的实施例描述了一种动态随机存取存储器（DRAM）装置，其可以中止自刷新模式以改善从自动刷新的DRAM低功率状态的退出时间。 在执行自刷新模式期间，DRAM设备可以从可操作地耦合到DRAM设备的存储器控制器接收信号（例如，器件使能信号）。 响应于接收到来自存储器控制器的信号，DRAM设备可以中止自刷新模式。
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公开(公告)号：US08938573B2
公开(公告)日：2015-01-20
申请号：US13539417
申请日：2012-06-30
申请人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
发明人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
IPC分类号： G06F12/06 , G11C11/406 , G06F11/30
CPC分类号： G06F11/3037 , G06F11/004 , G06F11/3471 , G06F2201/81 , G06F2201/88 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A system monitors data accesses to specific rows of memory to determine if a row hammer condition exists. The system can monitor accessed rows of memory to determine if the number of accesses to any of the rows exceeds a threshold associated with risk of data corruption on a row of memory physically adjacent to the row with high access. Based on the monitoring, a memory controller can determine if the number of accesses to a row exceeds the threshold, and indicate address information for the row whose access count reaches the threshold.
摘要翻译： 系统监视对特定行存储器的数据访问，以确定是否存在行锤条件。 该系统可以监视所访问的存储行，以确定对任何行的访问次数是否超过与物理上与高访问行相邻的存储体上的数据损坏风险相关联的阈值。 基于监视，存储器控制器可以确定对行的访问次数是否超过阈值，并且指示访问计数达到阈值的行的地址信息。
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公开(公告)号：US08806298B2
公开(公告)日：2014-08-12
申请号：US12824298
申请日：2010-06-28
申请人： Kuljit S. Bains
发明人： Kuljit S. Bains
IPC分类号： H03M13/00
CPC分类号： G06F11/1008
摘要： Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits. The memory device may also include error correction logic on the same die as the memory core. In some embodiments, the error correction logic enables the memory device to compute ECC bits and to compare the stored ECC bits with the computed ECC bits.
摘要翻译： 本发明的实施例一般涉及提高存储器件的可靠性，可用性和可服务性。 在一些实施例中，存储器设备包括具有存储数据位的第一部分的存储器核心和存储对应于数据位的纠错码（ECC）位的第二部分。 存储器件还可以包括与存储器核心相同的管芯上的纠错逻辑。 在一些实施例中，纠错逻辑使得存储器设备能够计算ECC比特并将所存储的ECC比特与所计算的ECC比特进行比较。
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公开(公告)号：US20140089576A1
公开(公告)日：2014-03-27
申请号：US13625741
申请日：2012-09-24
IPC分类号： G06F12/00
CPC分类号： G11C16/00 , G06F13/1636 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.
摘要翻译： 一个内存控制器，用于实现行锤事件潜在的受害者行的目标刷新。 在一个实施例中，存储器控制器接收指示存储器设备的特定行正经历重复访问，这威胁到与特定行物理相邻的一个或多个受害者行中的数据的完整性。 存储器控制器在没有指定存储器件的物理相邻行之间的偏移的地址映射信息的情况下访问默认偏移信息。 在另一个实施例中，存储器控制器基于默认偏移信息来确定潜在的受害者行的地址。 响应于所接收到的行锤事件的指示，存储器控制器向确定的多个地址中的每一个发送相应的命令给存储器设备，其中命令用于存储设备执行目标刷新潜在的受害者行。
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